xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra186 (and later) SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16  handles memory requests for 40-bit virtual addresses from internal clients
17  and arbitrates among them to allocate memory bandwidth.
18
19  Up to 15 GiB of physical memory can be supported. Security features such as
20  encryption of traffic to and from DRAM via general security apertures are
21  available for video and other secure applications, as well as DRAM ECC for
22  automotive safety applications (single bit error correction and double bit
23  error detection).
24
25properties:
26  $nodename:
27    pattern: "^memory-controller@[0-9a-f]+$"
28
29  compatible:
30    items:
31      - enum:
32          - nvidia,tegra186-mc
33          - nvidia,tegra194-mc
34          - nvidia,tegra234-mc
35          - nvidia,tegra264-mc
36
37  reg:
38    minItems: 6
39    maxItems: 18
40
41  reg-names:
42    minItems: 6
43    maxItems: 18
44
45  interrupts:
46    minItems: 1
47    maxItems: 8
48
49  interrupt-names:
50    minItems: 1
51    maxItems: 8
52
53  "#address-cells":
54    const: 2
55
56  "#size-cells":
57    const: 2
58
59  ranges: true
60
61  dma-ranges: true
62
63  "#interconnect-cells":
64    const: 1
65
66patternProperties:
67  "^external-memory-controller@[0-9a-f]+$":
68    description:
69      The bulk of the work involved in controlling the external memory
70      controller on NVIDIA Tegra186 and later is performed on the BPMP. This
71      coprocessor exposes the EMC clock that is used to set the frequency at
72      which the external memory is clocked and a remote procedure call that
73      can be used to obtain the set of available frequencies.
74    type: object
75    properties:
76      compatible:
77        items:
78          - enum:
79              - nvidia,tegra186-emc
80              - nvidia,tegra194-emc
81              - nvidia,tegra234-emc
82              - nvidia,tegra264-emc
83
84      reg:
85        minItems: 1
86        maxItems: 2
87
88      interrupts:
89        items:
90          - description: EMC general interrupt
91
92      clocks:
93        items:
94          - description: external memory clock
95
96      clock-names:
97        items:
98          - const: emc
99
100      "#interconnect-cells":
101        const: 0
102
103      nvidia,bpmp:
104        $ref: /schemas/types.yaml#/definitions/phandle
105        description:
106          phandle of the node representing the BPMP
107
108    allOf:
109      - if:
110          properties:
111            compatible:
112              const: nvidia,tegra186-emc
113        then:
114          properties:
115            reg:
116              maxItems: 1
117
118      - if:
119          properties:
120            compatible:
121              const: nvidia,tegra194-emc
122        then:
123          properties:
124            reg:
125              minItems: 2
126
127      - if:
128          properties:
129            compatible:
130              const: nvidia,tegra234-emc
131        then:
132          properties:
133            reg:
134              minItems: 2
135
136      - if:
137          properties:
138            compatible:
139              const: nvidia,tegra264-emc
140        then:
141          properties:
142            reg:
143              minItems: 2
144
145    additionalProperties: false
146
147    required:
148      - compatible
149      - reg
150      - interrupts
151      - clocks
152      - clock-names
153      - "#interconnect-cells"
154      - nvidia,bpmp
155
156allOf:
157  - if:
158      properties:
159        compatible:
160          const: nvidia,tegra186-mc
161    then:
162      properties:
163        reg:
164          maxItems: 6
165          description: 5 memory controller channels and 1 for stream-id registers
166
167        reg-names:
168          items:
169            - const: sid
170            - const: broadcast
171            - const: ch0
172            - const: ch1
173            - const: ch2
174            - const: ch3
175
176        interrupts:
177          items:
178            - description: MC general interrupt
179
180        interrupt-names: false
181
182  - if:
183      properties:
184        compatible:
185          const: nvidia,tegra194-mc
186    then:
187      properties:
188        reg:
189          minItems: 18
190          description: 17 memory controller channels and 1 for stream-id registers
191
192        reg-names:
193          items:
194            - const: sid
195            - const: broadcast
196            - const: ch0
197            - const: ch1
198            - const: ch2
199            - const: ch3
200            - const: ch4
201            - const: ch5
202            - const: ch6
203            - const: ch7
204            - const: ch8
205            - const: ch9
206            - const: ch10
207            - const: ch11
208            - const: ch12
209            - const: ch13
210            - const: ch14
211            - const: ch15
212
213        interrupts:
214          items:
215            - description: MC general interrupt
216
217        interrupt-names: false
218
219  - if:
220      properties:
221        compatible:
222          const: nvidia,tegra234-mc
223    then:
224      properties:
225        reg:
226          minItems: 18
227          description: 17 memory controller channels and 1 for stream-id registers
228
229        reg-names:
230          items:
231            - const: sid
232            - const: broadcast
233            - const: ch0
234            - const: ch1
235            - const: ch2
236            - const: ch3
237            - const: ch4
238            - const: ch5
239            - const: ch6
240            - const: ch7
241            - const: ch8
242            - const: ch9
243            - const: ch10
244            - const: ch11
245            - const: ch12
246            - const: ch13
247            - const: ch14
248            - const: ch15
249
250        interrupts:
251          items:
252            - description: MC general interrupt
253
254        interrupt-names: false
255
256  - if:
257      properties:
258        compatible:
259          const: nvidia,tegra264-mc
260    then:
261      properties:
262        reg:
263          minItems: 17
264          maxItems: 17
265          description: 17 memory controller channels
266
267        reg-names:
268          items:
269            - const: broadcast
270            - const: ch0
271            - const: ch1
272            - const: ch2
273            - const: ch3
274            - const: ch4
275            - const: ch5
276            - const: ch6
277            - const: ch7
278            - const: ch8
279            - const: ch9
280            - const: ch10
281            - const: ch11
282            - const: ch12
283            - const: ch13
284            - const: ch14
285            - const: ch15
286
287        interrupts:
288          minItems: 8
289          maxItems: 8
290          description: One interrupt line for each MC component
291
292        interrupt-names:
293          items:
294            - const: mcf
295            - const: hub1
296            - const: hub2
297            - const: hub3
298            - const: hub4
299            - const: hub5
300            - const: sbs
301            - const: channel
302
303additionalProperties: false
304
305required:
306  - compatible
307  - reg
308  - reg-names
309  - interrupts
310  - "#address-cells"
311  - "#size-cells"
312
313examples:
314  - |
315    #include <dt-bindings/clock/tegra186-clock.h>
316    #include <dt-bindings/interrupt-controller/arm-gic.h>
317
318    bus {
319        #address-cells = <2>;
320        #size-cells = <2>;
321
322        memory-controller@2c00000 {
323            compatible = "nvidia,tegra186-mc";
324            reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
325                  <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
326                  <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
327                  <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
328                  <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
329                  <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
330            reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
331            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
332
333            #address-cells = <2>;
334            #size-cells = <2>;
335
336            ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
337
338            /*
339             * Memory clients have access to all 40 bits that the memory
340             * controller can address.
341             */
342            dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
343
344            external-memory-controller@2c60000 {
345                compatible = "nvidia,tegra186-emc";
346                reg = <0x0 0x02c60000 0x0 0x50000>;
347                interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
348                clocks = <&bpmp TEGRA186_CLK_EMC>;
349                clock-names = "emc";
350
351                #interconnect-cells = <0>;
352
353                nvidia,bpmp = <&bpmp>;
354            };
355        };
356    };
357