xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml (revision ca220141fa8ebae09765a242076b2b77338106b0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra186 (and later) SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16  handles memory requests for 40-bit virtual addresses from internal clients
17  and arbitrates among them to allocate memory bandwidth.
18
19  Up to 15 GiB of physical memory can be supported. Security features such as
20  encryption of traffic to and from DRAM via general security apertures are
21  available for video and other secure applications, as well as DRAM ECC for
22  automotive safety applications (single bit error correction and double bit
23  error detection).
24
25properties:
26  $nodename:
27    pattern: "^memory-controller@[0-9a-f]+$"
28
29  compatible:
30    items:
31      - enum:
32          - nvidia,tegra186-mc
33          - nvidia,tegra194-mc
34          - nvidia,tegra234-mc
35          - nvidia,tegra264-mc
36
37  reg:
38    minItems: 6
39    maxItems: 18
40
41  reg-names:
42    minItems: 6
43    maxItems: 18
44
45  interrupts:
46    minItems: 1
47    maxItems: 8
48
49  interrupt-names:
50    minItems: 1
51    maxItems: 8
52
53  "#address-cells":
54    const: 2
55
56  "#size-cells":
57    const: 2
58
59  ranges: true
60
61  dma-ranges: true
62
63  "#interconnect-cells":
64    const: 1
65
66patternProperties:
67  "^external-memory-controller@[0-9a-f]+$":
68    description:
69      The bulk of the work involved in controlling the external memory
70      controller on NVIDIA Tegra186 and later is performed on the BPMP. This
71      coprocessor exposes the EMC clock that is used to set the frequency at
72      which the external memory is clocked and a remote procedure call that
73      can be used to obtain the set of available frequencies.
74    type: object
75    properties:
76      compatible:
77        items:
78          - enum:
79              - nvidia,tegra186-emc
80              - nvidia,tegra194-emc
81              - nvidia,tegra234-emc
82              - nvidia,tegra264-emc
83
84      reg:
85        minItems: 1
86        maxItems: 2
87
88      interrupts:
89        items:
90          - description: EMC general interrupt
91
92      clocks:
93        items:
94          - description: external memory clock
95          - description: data backbone clock
96        minItems: 1
97
98      clock-names:
99        items:
100          - const: emc
101          - const: dbb
102        minItems: 1
103
104      "#interconnect-cells":
105        const: 0
106
107      nvidia,bpmp:
108        $ref: /schemas/types.yaml#/definitions/phandle
109        description:
110          phandle of the node representing the BPMP
111
112    allOf:
113      - if:
114          properties:
115            compatible:
116              const: nvidia,tegra186-emc
117        then:
118          properties:
119            reg:
120              maxItems: 1
121
122            clocks:
123              maxItems: 1
124
125      - if:
126          properties:
127            compatible:
128              const: nvidia,tegra194-emc
129        then:
130          properties:
131            reg:
132              minItems: 2
133
134            clocks:
135              maxItems: 1
136
137      - if:
138          properties:
139            compatible:
140              const: nvidia,tegra234-emc
141        then:
142          properties:
143            reg:
144              minItems: 2
145
146            clocks:
147              maxItems: 1
148
149      - if:
150          properties:
151            compatible:
152              const: nvidia,tegra264-emc
153        then:
154          properties:
155            reg:
156              minItems: 2
157
158    additionalProperties: false
159
160    required:
161      - compatible
162      - reg
163      - interrupts
164      - clocks
165      - clock-names
166      - "#interconnect-cells"
167      - nvidia,bpmp
168
169allOf:
170  - if:
171      properties:
172        compatible:
173          const: nvidia,tegra186-mc
174    then:
175      properties:
176        reg:
177          maxItems: 6
178          description: 5 memory controller channels and 1 for stream-id registers
179
180        reg-names:
181          items:
182            - const: sid
183            - const: broadcast
184            - const: ch0
185            - const: ch1
186            - const: ch2
187            - const: ch3
188
189        interrupts:
190          items:
191            - description: MC general interrupt
192
193        interrupt-names: false
194
195  - if:
196      properties:
197        compatible:
198          const: nvidia,tegra194-mc
199    then:
200      properties:
201        reg:
202          minItems: 18
203          description: 17 memory controller channels and 1 for stream-id registers
204
205        reg-names:
206          items:
207            - const: sid
208            - const: broadcast
209            - const: ch0
210            - const: ch1
211            - const: ch2
212            - const: ch3
213            - const: ch4
214            - const: ch5
215            - const: ch6
216            - const: ch7
217            - const: ch8
218            - const: ch9
219            - const: ch10
220            - const: ch11
221            - const: ch12
222            - const: ch13
223            - const: ch14
224            - const: ch15
225
226        interrupts:
227          items:
228            - description: MC general interrupt
229
230        interrupt-names: false
231
232  - if:
233      properties:
234        compatible:
235          const: nvidia,tegra234-mc
236    then:
237      properties:
238        reg:
239          minItems: 18
240          description: 17 memory controller channels and 1 for stream-id registers
241
242        reg-names:
243          items:
244            - const: sid
245            - const: broadcast
246            - const: ch0
247            - const: ch1
248            - const: ch2
249            - const: ch3
250            - const: ch4
251            - const: ch5
252            - const: ch6
253            - const: ch7
254            - const: ch8
255            - const: ch9
256            - const: ch10
257            - const: ch11
258            - const: ch12
259            - const: ch13
260            - const: ch14
261            - const: ch15
262
263        interrupts:
264          items:
265            - description: MC general interrupt
266
267        interrupt-names: false
268
269  - if:
270      properties:
271        compatible:
272          const: nvidia,tegra264-mc
273    then:
274      properties:
275        reg:
276          minItems: 17
277          maxItems: 17
278          description: 17 memory controller channels
279
280        reg-names:
281          items:
282            - const: broadcast
283            - const: ch0
284            - const: ch1
285            - const: ch2
286            - const: ch3
287            - const: ch4
288            - const: ch5
289            - const: ch6
290            - const: ch7
291            - const: ch8
292            - const: ch9
293            - const: ch10
294            - const: ch11
295            - const: ch12
296            - const: ch13
297            - const: ch14
298            - const: ch15
299
300        interrupts:
301          minItems: 8
302          maxItems: 8
303          description: One interrupt line for each MC component
304
305        interrupt-names:
306          items:
307            - const: mcf
308            - const: hub1
309            - const: hub2
310            - const: hub3
311            - const: hub4
312            - const: hub5
313            - const: sbs
314            - const: channel
315
316additionalProperties: false
317
318required:
319  - compatible
320  - reg
321  - reg-names
322  - interrupts
323  - "#address-cells"
324  - "#size-cells"
325
326examples:
327  - |
328    #include <dt-bindings/clock/tegra186-clock.h>
329    #include <dt-bindings/interrupt-controller/arm-gic.h>
330
331    bus {
332        #address-cells = <2>;
333        #size-cells = <2>;
334
335        memory-controller@2c00000 {
336            compatible = "nvidia,tegra186-mc";
337            reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
338                  <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
339                  <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
340                  <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
341                  <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
342                  <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
343            reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
344            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
345
346            #address-cells = <2>;
347            #size-cells = <2>;
348
349            ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
350
351            /*
352             * Memory clients have access to all 40 bits that the memory
353             * controller can address.
354             */
355            dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
356
357            external-memory-controller@2c60000 {
358                compatible = "nvidia,tegra186-emc";
359                reg = <0x0 0x02c60000 0x0 0x50000>;
360                interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
361                clocks = <&bpmp TEGRA186_CLK_EMC>;
362                clock-names = "emc";
363
364                #interconnect-cells = <0>;
365
366                nvidia,bpmp = <&bpmp>;
367            };
368        };
369    };
370