xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml (revision bba2c3615bd6cfee7456d1130f2e6b01b3f4e9ba) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra186 (and later) SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16  handles memory requests for 40-bit virtual addresses from internal clients
17  and arbitrates among them to allocate memory bandwidth.
18
19  Up to 15 GiB of physical memory can be supported. Security features such as
20  encryption of traffic to and from DRAM via general security apertures are
21  available for video and other secure applications, as well as DRAM ECC for
22  automotive safety applications (single bit error correction and double bit
23  error detection).
24
25properties:
26  $nodename:
27    pattern: "^memory-controller@[0-9a-f]+$"
28
29  compatible:
30    items:
31      - enum:
32          - nvidia,tegra186-mc
33          - nvidia,tegra194-mc
34          - nvidia,tegra234-mc
35          - nvidia,tegra238-mc
36          - nvidia,tegra264-mc
37
38  reg:
39    minItems: 6
40    maxItems: 18
41
42  reg-names:
43    minItems: 6
44    maxItems: 18
45
46  interrupts:
47    minItems: 1
48    maxItems: 8
49
50  interrupt-names:
51    minItems: 1
52    maxItems: 8
53
54  "#address-cells":
55    const: 2
56
57  "#size-cells":
58    const: 2
59
60  ranges: true
61
62  dma-ranges: true
63
64  "#interconnect-cells":
65    const: 1
66
67patternProperties:
68  "^external-memory-controller@[0-9a-f]+$":
69    description:
70      The bulk of the work involved in controlling the external memory
71      controller on NVIDIA Tegra186 and later is performed on the BPMP. This
72      coprocessor exposes the EMC clock that is used to set the frequency at
73      which the external memory is clocked and a remote procedure call that
74      can be used to obtain the set of available frequencies.
75    type: object
76    properties:
77      compatible:
78        items:
79          - enum:
80              - nvidia,tegra186-emc
81              - nvidia,tegra194-emc
82              - nvidia,tegra234-emc
83              - nvidia,tegra264-emc
84
85      reg:
86        minItems: 1
87        maxItems: 2
88
89      interrupts:
90        items:
91          - description: EMC general interrupt
92
93      clocks:
94        items:
95          - description: external memory clock
96          - description: data backbone clock
97        minItems: 1
98
99      clock-names:
100        items:
101          - const: emc
102          - const: dbb
103        minItems: 1
104
105      "#interconnect-cells":
106        const: 0
107
108      nvidia,bpmp:
109        $ref: /schemas/types.yaml#/definitions/phandle
110        description:
111          phandle of the node representing the BPMP
112
113    allOf:
114      - if:
115          properties:
116            compatible:
117              const: nvidia,tegra186-emc
118        then:
119          properties:
120            reg:
121              maxItems: 1
122
123            clocks:
124              maxItems: 1
125
126      - if:
127          properties:
128            compatible:
129              const: nvidia,tegra194-emc
130        then:
131          properties:
132            reg:
133              minItems: 2
134
135            clocks:
136              maxItems: 1
137
138      - if:
139          properties:
140            compatible:
141              const: nvidia,tegra234-emc
142        then:
143          properties:
144            reg:
145              minItems: 2
146
147            clocks:
148              maxItems: 1
149
150      - if:
151          properties:
152            compatible:
153              const: nvidia,tegra264-emc
154        then:
155          properties:
156            reg:
157              minItems: 2
158
159    additionalProperties: false
160
161    required:
162      - compatible
163      - reg
164      - interrupts
165      - clocks
166      - clock-names
167      - "#interconnect-cells"
168      - nvidia,bpmp
169
170allOf:
171  - if:
172      properties:
173        compatible:
174          const: nvidia,tegra186-mc
175    then:
176      properties:
177        reg:
178          maxItems: 6
179          description: 5 memory controller channels and 1 for stream-id registers
180
181        reg-names:
182          items:
183            - const: sid
184            - const: broadcast
185            - const: ch0
186            - const: ch1
187            - const: ch2
188            - const: ch3
189
190        interrupts:
191          items:
192            - description: MC general interrupt
193
194        interrupt-names: false
195
196  - if:
197      properties:
198        compatible:
199          const: nvidia,tegra194-mc
200    then:
201      properties:
202        reg:
203          minItems: 18
204          description: 17 memory controller channels and 1 for stream-id registers
205
206        reg-names:
207          items:
208            - const: sid
209            - const: broadcast
210            - const: ch0
211            - const: ch1
212            - const: ch2
213            - const: ch3
214            - const: ch4
215            - const: ch5
216            - const: ch6
217            - const: ch7
218            - const: ch8
219            - const: ch9
220            - const: ch10
221            - const: ch11
222            - const: ch12
223            - const: ch13
224            - const: ch14
225            - const: ch15
226
227        interrupts:
228          items:
229            - description: MC general interrupt
230
231        interrupt-names: false
232
233  - if:
234      properties:
235        compatible:
236          const: nvidia,tegra234-mc
237    then:
238      properties:
239        reg:
240          minItems: 18
241          description: 17 memory controller channels and 1 for stream-id registers
242
243        reg-names:
244          items:
245            - const: sid
246            - const: broadcast
247            - const: ch0
248            - const: ch1
249            - const: ch2
250            - const: ch3
251            - const: ch4
252            - const: ch5
253            - const: ch6
254            - const: ch7
255            - const: ch8
256            - const: ch9
257            - const: ch10
258            - const: ch11
259            - const: ch12
260            - const: ch13
261            - const: ch14
262            - const: ch15
263
264        interrupts:
265          items:
266            - description: MC general interrupt
267
268        interrupt-names: false
269
270  - if:
271      properties:
272        compatible:
273          const: nvidia,tegra238-mc
274    then:
275      properties:
276        reg:
277          minItems: 10
278          maxItems: 10
279          description: 9 memory controller channels and 1 for stream-id registers
280
281        reg-names:
282          items:
283            - const: sid
284            - const: broadcast
285            - const: ch0
286            - const: ch1
287            - const: ch2
288            - const: ch3
289            - const: ch4
290            - const: ch5
291            - const: ch6
292            - const: ch7
293
294        interrupts:
295          items:
296            - description: MC general interrupt
297
298        interrupt-names: false
299
300  - if:
301      properties:
302        compatible:
303          const: nvidia,tegra264-mc
304    then:
305      properties:
306        reg:
307          minItems: 17
308          maxItems: 17
309          description: 17 memory controller channels
310
311        reg-names:
312          items:
313            - const: broadcast
314            - const: ch0
315            - const: ch1
316            - const: ch2
317            - const: ch3
318            - const: ch4
319            - const: ch5
320            - const: ch6
321            - const: ch7
322            - const: ch8
323            - const: ch9
324            - const: ch10
325            - const: ch11
326            - const: ch12
327            - const: ch13
328            - const: ch14
329            - const: ch15
330
331        interrupts:
332          minItems: 8
333          maxItems: 8
334          description: One interrupt line for each MC component
335
336        interrupt-names:
337          items:
338            - const: mcf
339            - const: hub1
340            - const: hub2
341            - const: hub3
342            - const: hub4
343            - const: hub5
344            - const: sbs
345            - const: channel
346
347additionalProperties: false
348
349required:
350  - compatible
351  - reg
352  - reg-names
353  - interrupts
354  - "#address-cells"
355  - "#size-cells"
356
357examples:
358  - |
359    #include <dt-bindings/clock/tegra186-clock.h>
360    #include <dt-bindings/interrupt-controller/arm-gic.h>
361
362    bus {
363        #address-cells = <2>;
364        #size-cells = <2>;
365
366        memory-controller@2c00000 {
367            compatible = "nvidia,tegra186-mc";
368            reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
369                  <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
370                  <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
371                  <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
372                  <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
373                  <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
374            reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
375            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
376
377            #address-cells = <2>;
378            #size-cells = <2>;
379
380            ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
381
382            /*
383             * Memory clients have access to all 40 bits that the memory
384             * controller can address.
385             */
386            dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
387
388            external-memory-controller@2c60000 {
389                compatible = "nvidia,tegra186-emc";
390                reg = <0x0 0x02c60000 0x0 0x50000>;
391                interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
392                clocks = <&bpmp TEGRA186_CLK_EMC>;
393                clock-names = "emc";
394
395                #interconnect-cells = <0>;
396
397                nvidia,bpmp = <&bpmp>;
398            };
399        };
400    };
401