xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml (revision bba2c3615bd6cfee7456d1130f2e6b01b3f4e9ba) 
1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
15  These are interleaved to provide high performance with the load shared across
16  two memory channels. The Tegra124 Memory Controller handles memory requests
17  from internal clients and arbitrates among them to allocate memory bandwidth
18  for DDR3L and LPDDR3 SDRAMs.
19
20properties:
21  compatible:
22    enum:
23      - nvidia,tegra114-mc
24      - nvidia,tegra124-mc
25
26  reg:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  clock-names:
33    items:
34      - const: mc
35
36  interrupts:
37    maxItems: 1
38
39  "#reset-cells":
40    const: 1
41
42  "#iommu-cells":
43    const: 1
44
45  "#interconnect-cells":
46    const: 1
47
48patternProperties:
49  "^emc-timings-[0-9]+$":
50    type: object
51    properties:
52      nvidia,ram-code:
53        $ref: /schemas/types.yaml#/definitions/uint32
54        description:
55          Value of RAM_CODE this timing set is used for.
56
57    patternProperties:
58      "^timing-[0-9]+$":
59        type: object
60        properties:
61          clock-frequency:
62            description:
63              Memory clock rate in Hz.
64            minimum: 1000000
65            maximum: 1066000000
66
67          nvidia,emem-configuration:
68            $ref: /schemas/types.yaml#/definitions/uint32-array
69            description:
70              Values to be written to the EMEM register block. See section
71              "20.11.1 MC Registers" in the Tegea114 TRM or
72              "15.6.1 MC Registers" in the Tegra124 TRM.
73            minItems: 18
74            maxItems: 19
75
76        required:
77          - clock-frequency
78          - nvidia,emem-configuration
79
80        additionalProperties: false
81
82    required:
83      - nvidia,ram-code
84
85    additionalProperties: false
86
87required:
88  - compatible
89  - reg
90  - interrupts
91  - clocks
92  - clock-names
93  - "#reset-cells"
94  - "#iommu-cells"
95  - "#interconnect-cells"
96
97additionalProperties: false
98
99examples:
100  - |
101    memory-controller@70019000 {
102        compatible = "nvidia,tegra124-mc";
103        reg = <0x70019000 0x1000>;
104        clocks = <&tegra_car 32>;
105        clock-names = "mc";
106
107        interrupts = <0 77 4>;
108
109        #iommu-cells = <1>;
110        #reset-cells = <1>;
111        #interconnect-cells = <1>;
112
113        emc-timings-3 {
114            nvidia,ram-code = <3>;
115
116            timing-12750000 {
117                clock-frequency = <12750000>;
118
119                nvidia,emem-configuration = <
120                    0x40040001 /* MC_EMEM_ARB_CFG */
121                    0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
122                    0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
123                    0x00000001 /* MC_EMEM_ARB_TIMING_RP */
124                    0x00000002 /* MC_EMEM_ARB_TIMING_RC */
125                    0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
126                    0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
127                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
128                    0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
129                    0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
130                    0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
131                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
132                    0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
133                    0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
134                    0x06030203 /* MC_EMEM_ARB_DA_TURNS */
135                    0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
136                    0x77e30303 /* MC_EMEM_ARB_MISC0 */
137                    0x70000f03 /* MC_EMEM_ARB_MISC1 */
138                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
139                >;
140            };
141        };
142    };
143