xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml (revision 5b193d6a8973655f19de87a7873ce31dee2d5fe6) 
1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
15  These are interleaved to provide high performance with the load shared across
16  two memory channels. The Tegra124 Memory Controller handles memory requests
17  from internal clients and arbitrates among them to allocate memory bandwidth
18  for DDR3L and LPDDR3 SDRAMs.
19
20properties:
21  compatible:
22    enum:
23      - nvidia,tegra114-mc
24      - nvidia,tegra124-mc
25      - nvidia,tegra132-mc
26
27  reg:
28    maxItems: 1
29
30  clocks:
31    maxItems: 1
32
33  clock-names:
34    items:
35      - const: mc
36
37  interrupts:
38    maxItems: 1
39
40  "#reset-cells":
41    const: 1
42
43  "#iommu-cells":
44    const: 1
45
46  "#interconnect-cells":
47    const: 1
48
49patternProperties:
50  "^emc-timings-[0-9]+$":
51    type: object
52    properties:
53      nvidia,ram-code:
54        $ref: /schemas/types.yaml#/definitions/uint32
55        description:
56          Value of RAM_CODE this timing set is used for.
57
58    patternProperties:
59      "^timing-[0-9]+$":
60        type: object
61        properties:
62          clock-frequency:
63            description:
64              Memory clock rate in Hz.
65            minimum: 1000000
66            maximum: 1066000000
67
68          nvidia,emem-configuration:
69            $ref: /schemas/types.yaml#/definitions/uint32-array
70            description:
71              Values to be written to the EMEM register block. See section
72              "20.11.1 MC Registers" in the Tegea114 TRM or
73              "15.6.1 MC Registers" in the Tegra124 TRM.
74            minItems: 18
75            maxItems: 19
76
77        required:
78          - clock-frequency
79          - nvidia,emem-configuration
80
81        additionalProperties: false
82
83    required:
84      - nvidia,ram-code
85
86    additionalProperties: false
87
88required:
89  - compatible
90  - reg
91  - interrupts
92  - clocks
93  - clock-names
94  - "#reset-cells"
95  - "#iommu-cells"
96  - "#interconnect-cells"
97
98additionalProperties: false
99
100examples:
101  - |
102    memory-controller@70019000 {
103        compatible = "nvidia,tegra124-mc";
104        reg = <0x70019000 0x1000>;
105        clocks = <&tegra_car 32>;
106        clock-names = "mc";
107
108        interrupts = <0 77 4>;
109
110        #iommu-cells = <1>;
111        #reset-cells = <1>;
112        #interconnect-cells = <1>;
113
114        emc-timings-3 {
115            nvidia,ram-code = <3>;
116
117            timing-12750000 {
118                clock-frequency = <12750000>;
119
120                nvidia,emem-configuration = <
121                    0x40040001 /* MC_EMEM_ARB_CFG */
122                    0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
123                    0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
124                    0x00000001 /* MC_EMEM_ARB_TIMING_RP */
125                    0x00000002 /* MC_EMEM_ARB_TIMING_RC */
126                    0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
127                    0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
128                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
129                    0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
130                    0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
131                    0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
132                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
133                    0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
134                    0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
135                    0x06030203 /* MC_EMEM_ARB_DA_TURNS */
136                    0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
137                    0x77e30303 /* MC_EMEM_ARB_MISC0 */
138                    0x70000f03 /* MC_EMEM_ARB_MISC1 */
139                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
140                >;
141            };
142        };
143    };
144