1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra124 SoC External Memory Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: | 14 The EMC interfaces with the off-chip SDRAM to service the request stream 15 sent from the memory controller. 16 17properties: 18 compatible: 19 enum: 20 - nvidia,tegra114-emc 21 - nvidia,tegra124-emc 22 23 reg: 24 maxItems: 1 25 26 clocks: 27 items: 28 - description: external memory clock 29 30 clock-names: 31 items: 32 - const: emc 33 34 interrupts: 35 maxItems: 1 36 37 "#interconnect-cells": 38 const: 0 39 40 nvidia,memory-controller: 41 $ref: /schemas/types.yaml#/definitions/phandle 42 description: 43 phandle of the memory controller node 44 45 power-domains: 46 maxItems: 1 47 description: 48 Phandle of the SoC "core" power domain. 49 50 operating-points-v2: 51 description: 52 Should contain freqs and voltages and opp-supported-hw property, which 53 is a bitfield indicating SoC speedo ID mask. 54 55patternProperties: 56 "^emc-timings-[0-9]+$": 57 type: object 58 additionalProperties: false 59 properties: 60 nvidia,ram-code: 61 $ref: /schemas/types.yaml#/definitions/uint32 62 description: 63 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that 64 this timing set is used for 65 66 patternProperties: 67 "^timing-[0-9]+$": 68 type: object 69 properties: 70 clock-frequency: 71 description: 72 external memory clock rate in Hz 73 minimum: 1000000 74 maximum: 1000000000 75 76 nvidia,emc-auto-cal-config: 77 $ref: /schemas/types.yaml#/definitions/uint32 78 description: 79 value of the EMC_AUTO_CAL_CONFIG register for this set of 80 timings 81 82 nvidia,emc-auto-cal-config2: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: 85 value of the EMC_AUTO_CAL_CONFIG2 register for this set of 86 timings 87 88 nvidia,emc-auto-cal-config3: 89 $ref: /schemas/types.yaml#/definitions/uint32 90 description: 91 value of the EMC_AUTO_CAL_CONFIG3 register for this set of 92 timings 93 94 nvidia,emc-auto-cal-interval: 95 description: 96 pad calibration interval in microseconds 97 $ref: /schemas/types.yaml#/definitions/uint32 98 minimum: 0 99 maximum: 2097151 100 101 nvidia,emc-bgbias-ctl0: 102 $ref: /schemas/types.yaml#/definitions/uint32 103 description: 104 value of the EMC_BGBIAS_CTL0 register for this set of timings 105 106 nvidia,emc-cfg: 107 $ref: /schemas/types.yaml#/definitions/uint32 108 description: 109 value of the EMC_CFG register for this set of timings 110 111 nvidia,emc-cfg-2: 112 $ref: /schemas/types.yaml#/definitions/uint32 113 description: 114 value of the EMC_CFG_2 register for this set of timings 115 116 nvidia,emc-ctt-term-ctrl: 117 $ref: /schemas/types.yaml#/definitions/uint32 118 description: 119 value of the EMC_CTT_TERM_CTRL register for this set of timings 120 121 nvidia,emc-mode-1: 122 $ref: /schemas/types.yaml#/definitions/uint32 123 description: 124 value of the EMC_MRW register for this set of timings 125 126 nvidia,emc-mode-2: 127 $ref: /schemas/types.yaml#/definitions/uint32 128 description: 129 value of the EMC_MRW2 register for this set of timings 130 131 nvidia,emc-mode-4: 132 $ref: /schemas/types.yaml#/definitions/uint32 133 description: 134 value of the EMC_MRW4 register for this set of timings 135 136 nvidia,emc-mode-reset: 137 $ref: /schemas/types.yaml#/definitions/uint32 138 description: 139 reset value of the EMC_MRS register for this set of timings 140 141 nvidia,emc-mrs-wait-cnt: 142 $ref: /schemas/types.yaml#/definitions/uint32 143 description: 144 value of the EMR_MRS_WAIT_CNT register for this set of timings 145 146 nvidia,emc-sel-dpd-ctrl: 147 $ref: /schemas/types.yaml#/definitions/uint32 148 description: 149 value of the EMC_SEL_DPD_CTRL register for this set of timings 150 151 nvidia,emc-xm2dqspadctrl2: 152 $ref: /schemas/types.yaml#/definitions/uint32 153 description: 154 value of the EMC_XM2DQSPADCTRL2 register for this set of timings 155 156 nvidia,emc-zcal-cnt-long: 157 description: 158 number of EMC clocks to wait before issuing any commands after 159 clock change 160 $ref: /schemas/types.yaml#/definitions/uint32 161 minimum: 0 162 maximum: 1023 163 164 nvidia,emc-zcal-interval: 165 $ref: /schemas/types.yaml#/definitions/uint32 166 description: 167 value of the EMC_ZCAL_INTERVAL register for this set of timings 168 169 nvidia,emc-configuration: 170 description: 171 EMC timing characterization data. These are the registers (see 172 section "20.11.2 EMC Registers" in the Tegra114 TRM or section 173 "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to 174 be specified, according to the board documentation. 175 $ref: /schemas/types.yaml#/definitions/uint32-array 176 minItems: 97 177 maxItems: 143 178 179 required: 180 - clock-frequency 181 - nvidia,emc-auto-cal-config 182 - nvidia,emc-auto-cal-config2 183 - nvidia,emc-auto-cal-config3 184 - nvidia,emc-auto-cal-interval 185 - nvidia,emc-cfg 186 - nvidia,emc-ctt-term-ctrl 187 - nvidia,emc-mode-1 188 - nvidia,emc-mode-2 189 - nvidia,emc-mode-4 190 - nvidia,emc-mode-reset 191 - nvidia,emc-mrs-wait-cnt 192 - nvidia,emc-sel-dpd-ctrl 193 - nvidia,emc-xm2dqspadctrl2 194 - nvidia,emc-zcal-cnt-long 195 - nvidia,emc-zcal-interval 196 - nvidia,emc-configuration 197 198 additionalProperties: false 199 200required: 201 - compatible 202 - reg 203 - clocks 204 - clock-names 205 - nvidia,memory-controller 206 - "#interconnect-cells" 207 - operating-points-v2 208 209allOf: 210 - if: 211 properties: 212 compatible: 213 contains: 214 enum: 215 - nvidia,tegra124-emc 216 then: 217 patternProperties: 218 "^emc-timings-[0-9]+$": 219 patternProperties: 220 "^timing-[0-9]+$": 221 required: 222 - nvidia,emc-bgbias-ctl0 223 - nvidia,emc-cfg-2 224 225additionalProperties: false 226 227examples: 228 - | 229 #include <dt-bindings/clock/tegra124-car.h> 230 #include <dt-bindings/interrupt-controller/arm-gic.h> 231 232 mc: memory-controller@70019000 { 233 compatible = "nvidia,tegra124-mc"; 234 reg = <0x70019000 0x1000>; 235 clocks = <&tegra_car TEGRA124_CLK_MC>; 236 clock-names = "mc"; 237 238 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 239 240 #iommu-cells = <1>; 241 #reset-cells = <1>; 242 #interconnect-cells = <1>; 243 }; 244 245 external-memory-controller@7001b000 { 246 compatible = "nvidia,tegra124-emc"; 247 reg = <0x7001b000 0x1000>; 248 clocks = <&car TEGRA124_CLK_EMC>; 249 clock-names = "emc"; 250 251 nvidia,memory-controller = <&mc>; 252 operating-points-v2 = <&dvfs_opp_table>; 253 power-domains = <&domain>; 254 255 #interconnect-cells = <0>; 256 257 emc-timings-0 { 258 nvidia,ram-code = <3>; 259 260 timing-0 { 261 clock-frequency = <12750000>; 262 263 nvidia,emc-auto-cal-config = <0xa1430000>; 264 nvidia,emc-auto-cal-config2 = <0x00000000>; 265 nvidia,emc-auto-cal-config3 = <0x00000000>; 266 nvidia,emc-auto-cal-interval = <0x001fffff>; 267 nvidia,emc-bgbias-ctl0 = <0x00000008>; 268 nvidia,emc-cfg = <0x73240000>; 269 nvidia,emc-cfg-2 = <0x000008c5>; 270 nvidia,emc-ctt-term-ctrl = <0x00000802>; 271 nvidia,emc-mode-1 = <0x80100003>; 272 nvidia,emc-mode-2 = <0x80200008>; 273 nvidia,emc-mode-4 = <0x00000000>; 274 nvidia,emc-mode-reset = <0x80001221>; 275 nvidia,emc-mrs-wait-cnt = <0x000e000e>; 276 nvidia,emc-sel-dpd-ctrl = <0x00040128>; 277 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; 278 nvidia,emc-zcal-cnt-long = <0x00000042>; 279 nvidia,emc-zcal-interval = <0x00000000>; 280 281 nvidia,emc-configuration = < 282 0x00000000 /* EMC_RC */ 283 0x00000003 /* EMC_RFC */ 284 0x00000000 /* EMC_RFC_SLR */ 285 0x00000000 /* EMC_RAS */ 286 0x00000000 /* EMC_RP */ 287 0x00000004 /* EMC_R2W */ 288 0x0000000a /* EMC_W2R */ 289 0x00000003 /* EMC_R2P */ 290 0x0000000b /* EMC_W2P */ 291 0x00000000 /* EMC_RD_RCD */ 292 0x00000000 /* EMC_WR_RCD */ 293 0x00000003 /* EMC_RRD */ 294 0x00000003 /* EMC_REXT */ 295 0x00000000 /* EMC_WEXT */ 296 0x00000006 /* EMC_WDV */ 297 0x00000006 /* EMC_WDV_MASK */ 298 0x00000006 /* EMC_QUSE */ 299 0x00000002 /* EMC_QUSE_WIDTH */ 300 0x00000000 /* EMC_IBDLY */ 301 0x00000005 /* EMC_EINPUT */ 302 0x00000005 /* EMC_EINPUT_DURATION */ 303 0x00010000 /* EMC_PUTERM_EXTRA */ 304 0x00000003 /* EMC_PUTERM_WIDTH */ 305 0x00000000 /* EMC_PUTERM_ADJ */ 306 0x00000000 /* EMC_CDB_CNTL_1 */ 307 0x00000000 /* EMC_CDB_CNTL_2 */ 308 0x00000000 /* EMC_CDB_CNTL_3 */ 309 0x00000004 /* EMC_QRST */ 310 0x0000000c /* EMC_QSAFE */ 311 0x0000000d /* EMC_RDV */ 312 0x0000000f /* EMC_RDV_MASK */ 313 0x00000060 /* EMC_REFRESH */ 314 0x00000000 /* EMC_BURST_REFRESH_NUM */ 315 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ 316 0x00000002 /* EMC_PDEX2WR */ 317 0x00000002 /* EMC_PDEX2RD */ 318 0x00000001 /* EMC_PCHG2PDEN */ 319 0x00000000 /* EMC_ACT2PDEN */ 320 0x00000007 /* EMC_AR2PDEN */ 321 0x0000000f /* EMC_RW2PDEN */ 322 0x00000005 /* EMC_TXSR */ 323 0x00000005 /* EMC_TXSRDLL */ 324 0x00000004 /* EMC_TCKE */ 325 0x00000005 /* EMC_TCKESR */ 326 0x00000004 /* EMC_TPD */ 327 0x00000000 /* EMC_TFAW */ 328 0x00000000 /* EMC_TRPAB */ 329 0x00000005 /* EMC_TCLKSTABLE */ 330 0x00000005 /* EMC_TCLKSTOP */ 331 0x00000064 /* EMC_TREFBW */ 332 0x00000000 /* EMC_FBIO_CFG6 */ 333 0x00000000 /* EMC_ODT_WRITE */ 334 0x00000000 /* EMC_ODT_READ */ 335 0x106aa298 /* EMC_FBIO_CFG5 */ 336 0x002c00a0 /* EMC_CFG_DIG_DLL */ 337 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 338 0x00064000 /* EMC_DLL_XFORM_DQS0 */ 339 0x00064000 /* EMC_DLL_XFORM_DQS1 */ 340 0x00064000 /* EMC_DLL_XFORM_DQS2 */ 341 0x00064000 /* EMC_DLL_XFORM_DQS3 */ 342 0x00064000 /* EMC_DLL_XFORM_DQS4 */ 343 0x00064000 /* EMC_DLL_XFORM_DQS5 */ 344 0x00064000 /* EMC_DLL_XFORM_DQS6 */ 345 0x00064000 /* EMC_DLL_XFORM_DQS7 */ 346 0x00064000 /* EMC_DLL_XFORM_DQS8 */ 347 0x00064000 /* EMC_DLL_XFORM_DQS9 */ 348 0x00064000 /* EMC_DLL_XFORM_DQS10 */ 349 0x00064000 /* EMC_DLL_XFORM_DQS11 */ 350 0x00064000 /* EMC_DLL_XFORM_DQS12 */ 351 0x00064000 /* EMC_DLL_XFORM_DQS13 */ 352 0x00064000 /* EMC_DLL_XFORM_DQS14 */ 353 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 354 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 355 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 356 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 357 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 358 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 359 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 360 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 361 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 362 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ 363 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ 364 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ 365 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ 366 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ 367 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ 368 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 369 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 370 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ 371 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ 372 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ 373 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 374 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 375 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ 376 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 377 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 378 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 379 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 380 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 381 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 382 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 383 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 384 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ 385 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ 386 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ 387 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ 388 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ 389 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 390 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 391 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ 392 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 393 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 394 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 395 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 396 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ 397 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ 398 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ 399 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 400 0x10000280 /* EMC_XM2CMDPADCTRL */ 401 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 402 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 403 0x00000000 /* EMC_XM2DQPADCTRL2 */ 404 0x00000000 /* EMC_XM2DQPADCTRL3 */ 405 0x77ffc081 /* EMC_XM2CLKPADCTRL */ 406 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ 407 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 408 0x07070004 /* EMC_XM2VTTGENPADCTRL */ 409 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 410 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ 411 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 412 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 413 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 414 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 415 0x0000003f /* EMC_DSR_VTTGEN_DRV */ 416 0x00000007 /* EMC_TXDSRVTTGEN */ 417 0x00000000 /* EMC_FBIO_SPARE */ 418 0x00000042 /* EMC_ZCAL_WAIT_CNT */ 419 0x000e000e /* EMC_MRS_WAIT_CNT2 */ 420 0x00000000 /* EMC_CTT */ 421 0x00000003 /* EMC_CTT_DURATION */ 422 0x0000f2f3 /* EMC_CFG_PIPE */ 423 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ 424 0x0000000a /* EMC_QPOP */ 425 >; 426 }; 427 }; 428 }; 429