1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra124 SoC External Memory Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: | 14 The EMC interfaces with the off-chip SDRAM to service the request stream 15 sent from the memory controller. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - nvidia,tegra114-emc 22 - nvidia,tegra124-emc 23 - items: 24 - const: nvidia,tegra132-emc 25 - const: nvidia,tegra124-emc 26 27 reg: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: external memory clock 33 34 clock-names: 35 items: 36 - const: emc 37 38 interrupts: 39 maxItems: 1 40 41 "#interconnect-cells": 42 const: 0 43 44 nvidia,memory-controller: 45 $ref: /schemas/types.yaml#/definitions/phandle 46 description: 47 phandle of the memory controller node 48 49 power-domains: 50 maxItems: 1 51 description: 52 Phandle of the SoC "core" power domain. 53 54 operating-points-v2: 55 description: 56 Should contain freqs and voltages and opp-supported-hw property, which 57 is a bitfield indicating SoC speedo ID mask. 58 59patternProperties: 60 "^emc-timings-[0-9]+$": 61 type: object 62 additionalProperties: false 63 properties: 64 nvidia,ram-code: 65 $ref: /schemas/types.yaml#/definitions/uint32 66 description: 67 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that 68 this timing set is used for 69 70 patternProperties: 71 "^timing-[0-9]+$": 72 type: object 73 properties: 74 clock-frequency: 75 description: 76 external memory clock rate in Hz 77 minimum: 1000000 78 maximum: 1000000000 79 80 nvidia,emc-auto-cal-config: 81 $ref: /schemas/types.yaml#/definitions/uint32 82 description: 83 value of the EMC_AUTO_CAL_CONFIG register for this set of 84 timings 85 86 nvidia,emc-auto-cal-config2: 87 $ref: /schemas/types.yaml#/definitions/uint32 88 description: 89 value of the EMC_AUTO_CAL_CONFIG2 register for this set of 90 timings 91 92 nvidia,emc-auto-cal-config3: 93 $ref: /schemas/types.yaml#/definitions/uint32 94 description: 95 value of the EMC_AUTO_CAL_CONFIG3 register for this set of 96 timings 97 98 nvidia,emc-auto-cal-interval: 99 description: 100 pad calibration interval in microseconds 101 $ref: /schemas/types.yaml#/definitions/uint32 102 minimum: 0 103 maximum: 2097151 104 105 nvidia,emc-bgbias-ctl0: 106 $ref: /schemas/types.yaml#/definitions/uint32 107 description: 108 value of the EMC_BGBIAS_CTL0 register for this set of timings 109 110 nvidia,emc-cfg: 111 $ref: /schemas/types.yaml#/definitions/uint32 112 description: 113 value of the EMC_CFG register for this set of timings 114 115 nvidia,emc-cfg-2: 116 $ref: /schemas/types.yaml#/definitions/uint32 117 description: 118 value of the EMC_CFG_2 register for this set of timings 119 120 nvidia,emc-ctt-term-ctrl: 121 $ref: /schemas/types.yaml#/definitions/uint32 122 description: 123 value of the EMC_CTT_TERM_CTRL register for this set of timings 124 125 nvidia,emc-mode-1: 126 $ref: /schemas/types.yaml#/definitions/uint32 127 description: 128 value of the EMC_MRW register for this set of timings 129 130 nvidia,emc-mode-2: 131 $ref: /schemas/types.yaml#/definitions/uint32 132 description: 133 value of the EMC_MRW2 register for this set of timings 134 135 nvidia,emc-mode-4: 136 $ref: /schemas/types.yaml#/definitions/uint32 137 description: 138 value of the EMC_MRW4 register for this set of timings 139 140 nvidia,emc-mode-reset: 141 $ref: /schemas/types.yaml#/definitions/uint32 142 description: 143 reset value of the EMC_MRS register for this set of timings 144 145 nvidia,emc-mrs-wait-cnt: 146 $ref: /schemas/types.yaml#/definitions/uint32 147 description: 148 value of the EMR_MRS_WAIT_CNT register for this set of timings 149 150 nvidia,emc-sel-dpd-ctrl: 151 $ref: /schemas/types.yaml#/definitions/uint32 152 description: 153 value of the EMC_SEL_DPD_CTRL register for this set of timings 154 155 nvidia,emc-xm2dqspadctrl2: 156 $ref: /schemas/types.yaml#/definitions/uint32 157 description: 158 value of the EMC_XM2DQSPADCTRL2 register for this set of timings 159 160 nvidia,emc-zcal-cnt-long: 161 description: 162 number of EMC clocks to wait before issuing any commands after 163 clock change 164 $ref: /schemas/types.yaml#/definitions/uint32 165 minimum: 0 166 maximum: 1023 167 168 nvidia,emc-zcal-interval: 169 $ref: /schemas/types.yaml#/definitions/uint32 170 description: 171 value of the EMC_ZCAL_INTERVAL register for this set of timings 172 173 nvidia,emc-configuration: 174 description: 175 EMC timing characterization data. These are the registers (see 176 section "20.11.2 EMC Registers" in the Tegra114 TRM or section 177 "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to 178 be specified, according to the board documentation. 179 $ref: /schemas/types.yaml#/definitions/uint32-array 180 minItems: 97 181 maxItems: 143 182 183 required: 184 - clock-frequency 185 - nvidia,emc-auto-cal-config 186 - nvidia,emc-auto-cal-config2 187 - nvidia,emc-auto-cal-config3 188 - nvidia,emc-auto-cal-interval 189 - nvidia,emc-cfg 190 - nvidia,emc-ctt-term-ctrl 191 - nvidia,emc-mode-1 192 - nvidia,emc-mode-2 193 - nvidia,emc-mode-4 194 - nvidia,emc-mode-reset 195 - nvidia,emc-mrs-wait-cnt 196 - nvidia,emc-sel-dpd-ctrl 197 - nvidia,emc-xm2dqspadctrl2 198 - nvidia,emc-zcal-cnt-long 199 - nvidia,emc-zcal-interval 200 - nvidia,emc-configuration 201 202 additionalProperties: false 203 204required: 205 - compatible 206 - reg 207 - clocks 208 - clock-names 209 - nvidia,memory-controller 210 - "#interconnect-cells" 211 - operating-points-v2 212 213allOf: 214 - if: 215 properties: 216 compatible: 217 contains: 218 enum: 219 - nvidia,tegra124-emc 220 then: 221 patternProperties: 222 "^emc-timings-[0-9]+$": 223 patternProperties: 224 "^timing-[0-9]+$": 225 required: 226 - nvidia,emc-bgbias-ctl0 227 - nvidia,emc-cfg-2 228 229additionalProperties: false 230 231examples: 232 - | 233 #include <dt-bindings/clock/tegra124-car.h> 234 #include <dt-bindings/interrupt-controller/arm-gic.h> 235 236 mc: memory-controller@70019000 { 237 compatible = "nvidia,tegra124-mc"; 238 reg = <0x70019000 0x1000>; 239 clocks = <&tegra_car TEGRA124_CLK_MC>; 240 clock-names = "mc"; 241 242 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 243 244 #iommu-cells = <1>; 245 #reset-cells = <1>; 246 #interconnect-cells = <1>; 247 }; 248 249 external-memory-controller@7001b000 { 250 compatible = "nvidia,tegra124-emc"; 251 reg = <0x7001b000 0x1000>; 252 clocks = <&car TEGRA124_CLK_EMC>; 253 clock-names = "emc"; 254 255 nvidia,memory-controller = <&mc>; 256 operating-points-v2 = <&dvfs_opp_table>; 257 power-domains = <&domain>; 258 259 #interconnect-cells = <0>; 260 261 emc-timings-0 { 262 nvidia,ram-code = <3>; 263 264 timing-0 { 265 clock-frequency = <12750000>; 266 267 nvidia,emc-auto-cal-config = <0xa1430000>; 268 nvidia,emc-auto-cal-config2 = <0x00000000>; 269 nvidia,emc-auto-cal-config3 = <0x00000000>; 270 nvidia,emc-auto-cal-interval = <0x001fffff>; 271 nvidia,emc-bgbias-ctl0 = <0x00000008>; 272 nvidia,emc-cfg = <0x73240000>; 273 nvidia,emc-cfg-2 = <0x000008c5>; 274 nvidia,emc-ctt-term-ctrl = <0x00000802>; 275 nvidia,emc-mode-1 = <0x80100003>; 276 nvidia,emc-mode-2 = <0x80200008>; 277 nvidia,emc-mode-4 = <0x00000000>; 278 nvidia,emc-mode-reset = <0x80001221>; 279 nvidia,emc-mrs-wait-cnt = <0x000e000e>; 280 nvidia,emc-sel-dpd-ctrl = <0x00040128>; 281 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; 282 nvidia,emc-zcal-cnt-long = <0x00000042>; 283 nvidia,emc-zcal-interval = <0x00000000>; 284 285 nvidia,emc-configuration = < 286 0x00000000 /* EMC_RC */ 287 0x00000003 /* EMC_RFC */ 288 0x00000000 /* EMC_RFC_SLR */ 289 0x00000000 /* EMC_RAS */ 290 0x00000000 /* EMC_RP */ 291 0x00000004 /* EMC_R2W */ 292 0x0000000a /* EMC_W2R */ 293 0x00000003 /* EMC_R2P */ 294 0x0000000b /* EMC_W2P */ 295 0x00000000 /* EMC_RD_RCD */ 296 0x00000000 /* EMC_WR_RCD */ 297 0x00000003 /* EMC_RRD */ 298 0x00000003 /* EMC_REXT */ 299 0x00000000 /* EMC_WEXT */ 300 0x00000006 /* EMC_WDV */ 301 0x00000006 /* EMC_WDV_MASK */ 302 0x00000006 /* EMC_QUSE */ 303 0x00000002 /* EMC_QUSE_WIDTH */ 304 0x00000000 /* EMC_IBDLY */ 305 0x00000005 /* EMC_EINPUT */ 306 0x00000005 /* EMC_EINPUT_DURATION */ 307 0x00010000 /* EMC_PUTERM_EXTRA */ 308 0x00000003 /* EMC_PUTERM_WIDTH */ 309 0x00000000 /* EMC_PUTERM_ADJ */ 310 0x00000000 /* EMC_CDB_CNTL_1 */ 311 0x00000000 /* EMC_CDB_CNTL_2 */ 312 0x00000000 /* EMC_CDB_CNTL_3 */ 313 0x00000004 /* EMC_QRST */ 314 0x0000000c /* EMC_QSAFE */ 315 0x0000000d /* EMC_RDV */ 316 0x0000000f /* EMC_RDV_MASK */ 317 0x00000060 /* EMC_REFRESH */ 318 0x00000000 /* EMC_BURST_REFRESH_NUM */ 319 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ 320 0x00000002 /* EMC_PDEX2WR */ 321 0x00000002 /* EMC_PDEX2RD */ 322 0x00000001 /* EMC_PCHG2PDEN */ 323 0x00000000 /* EMC_ACT2PDEN */ 324 0x00000007 /* EMC_AR2PDEN */ 325 0x0000000f /* EMC_RW2PDEN */ 326 0x00000005 /* EMC_TXSR */ 327 0x00000005 /* EMC_TXSRDLL */ 328 0x00000004 /* EMC_TCKE */ 329 0x00000005 /* EMC_TCKESR */ 330 0x00000004 /* EMC_TPD */ 331 0x00000000 /* EMC_TFAW */ 332 0x00000000 /* EMC_TRPAB */ 333 0x00000005 /* EMC_TCLKSTABLE */ 334 0x00000005 /* EMC_TCLKSTOP */ 335 0x00000064 /* EMC_TREFBW */ 336 0x00000000 /* EMC_FBIO_CFG6 */ 337 0x00000000 /* EMC_ODT_WRITE */ 338 0x00000000 /* EMC_ODT_READ */ 339 0x106aa298 /* EMC_FBIO_CFG5 */ 340 0x002c00a0 /* EMC_CFG_DIG_DLL */ 341 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 342 0x00064000 /* EMC_DLL_XFORM_DQS0 */ 343 0x00064000 /* EMC_DLL_XFORM_DQS1 */ 344 0x00064000 /* EMC_DLL_XFORM_DQS2 */ 345 0x00064000 /* EMC_DLL_XFORM_DQS3 */ 346 0x00064000 /* EMC_DLL_XFORM_DQS4 */ 347 0x00064000 /* EMC_DLL_XFORM_DQS5 */ 348 0x00064000 /* EMC_DLL_XFORM_DQS6 */ 349 0x00064000 /* EMC_DLL_XFORM_DQS7 */ 350 0x00064000 /* EMC_DLL_XFORM_DQS8 */ 351 0x00064000 /* EMC_DLL_XFORM_DQS9 */ 352 0x00064000 /* EMC_DLL_XFORM_DQS10 */ 353 0x00064000 /* EMC_DLL_XFORM_DQS11 */ 354 0x00064000 /* EMC_DLL_XFORM_DQS12 */ 355 0x00064000 /* EMC_DLL_XFORM_DQS13 */ 356 0x00064000 /* EMC_DLL_XFORM_DQS14 */ 357 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 358 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 359 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 360 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 361 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 362 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 363 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 364 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 365 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 366 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ 367 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ 368 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ 369 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ 370 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ 371 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ 372 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 373 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 374 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ 375 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ 376 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ 377 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 378 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 379 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ 380 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 381 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 382 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 383 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 384 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 385 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 386 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 387 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 388 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ 389 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ 390 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ 391 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ 392 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ 393 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 394 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 395 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ 396 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 397 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 398 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 399 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 400 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ 401 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ 402 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ 403 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 404 0x10000280 /* EMC_XM2CMDPADCTRL */ 405 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 406 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 407 0x00000000 /* EMC_XM2DQPADCTRL2 */ 408 0x00000000 /* EMC_XM2DQPADCTRL3 */ 409 0x77ffc081 /* EMC_XM2CLKPADCTRL */ 410 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ 411 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 412 0x07070004 /* EMC_XM2VTTGENPADCTRL */ 413 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 414 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ 415 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 416 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 417 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 418 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 419 0x0000003f /* EMC_DSR_VTTGEN_DRV */ 420 0x00000007 /* EMC_TXDSRVTTGEN */ 421 0x00000000 /* EMC_FBIO_SPARE */ 422 0x00000042 /* EMC_ZCAL_WAIT_CNT */ 423 0x000e000e /* EMC_MRS_WAIT_CNT2 */ 424 0x00000000 /* EMC_CTT */ 425 0x00000003 /* EMC_CTT_DURATION */ 426 0x0000f2f3 /* EMC_CFG_PIPE */ 427 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ 428 0x0000000a /* EMC_QPOP */ 429 >; 430 }; 431 }; 432 }; 433