xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml (revision 77346a704c913268a2dad68d59523fd85dc74088) 
1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra30 SoC Memory Controller
8
9maintainers:
10  - Dmitry Osipenko <digetx@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <thierry.reding@gmail.com>
13
14description: |
15  Tegra30 Memory Controller architecturally consists of the following parts:
16
17    Arbitration Domains, which can handle a single request or response per
18    clock from a group of clients. Typically, a system has a single Arbitration
19    Domain, but an implementation may divide the client space into multiple
20    Arbitration Domains to increase the effective system bandwidth.
21
22    Protocol Arbiter, which manage a related pool of memory devices. A system
23    may have a single Protocol Arbiter or multiple Protocol Arbiters.
24
25    Memory Crossbar, which routes request and responses between Arbitration
26    Domains and Protocol Arbiters. In the simplest version of the system, the
27    Memory Crossbar is just a pass through between a single Arbitration Domain
28    and a single Protocol Arbiter.
29
30    Global Resources, which include things like configuration registers which
31    are shared across the Memory Subsystem.
32
33  The Tegra30 Memory Controller handles memory requests from internal clients
34  and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
35  SDRAMs.
36
37properties:
38  compatible:
39    const: nvidia,tegra30-mc
40
41  reg:
42    maxItems: 1
43
44  clocks:
45    maxItems: 1
46
47  clock-names:
48    items:
49      - const: mc
50
51  interrupts:
52    maxItems: 1
53
54  "#reset-cells":
55    const: 1
56
57  "#iommu-cells":
58    const: 1
59
60patternProperties:
61  "^emc-timings-[0-9]+$":
62    type: object
63    properties:
64      nvidia,ram-code:
65        $ref: /schemas/types.yaml#/definitions/uint32
66        description:
67          Value of RAM_CODE this timing set is used for.
68
69    patternProperties:
70      "^timing-[0-9]+$":
71        type: object
72        properties:
73          clock-frequency:
74            description:
75              Memory clock rate in Hz.
76            minimum: 1000000
77            maximum: 900000000
78
79          nvidia,emem-configuration:
80            $ref: /schemas/types.yaml#/definitions/uint32-array
81            description: |
82              Values to be written to the EMEM register block. See section
83              "18.13.1 MC Registers" in the TRM.
84            items:
85              - description: MC_EMEM_ARB_CFG
86              - description: MC_EMEM_ARB_OUTSTANDING_REQ
87              - description: MC_EMEM_ARB_TIMING_RCD
88              - description: MC_EMEM_ARB_TIMING_RP
89              - description: MC_EMEM_ARB_TIMING_RC
90              - description: MC_EMEM_ARB_TIMING_RAS
91              - description: MC_EMEM_ARB_TIMING_FAW
92              - description: MC_EMEM_ARB_TIMING_RRD
93              - description: MC_EMEM_ARB_TIMING_RAP2PRE
94              - description: MC_EMEM_ARB_TIMING_WAP2PRE
95              - description: MC_EMEM_ARB_TIMING_R2R
96              - description: MC_EMEM_ARB_TIMING_W2W
97              - description: MC_EMEM_ARB_TIMING_R2W
98              - description: MC_EMEM_ARB_TIMING_W2R
99              - description: MC_EMEM_ARB_DA_TURNS
100              - description: MC_EMEM_ARB_DA_COVERS
101              - description: MC_EMEM_ARB_MISC0
102              - description: MC_EMEM_ARB_RING1_THROTTLE
103
104        required:
105          - clock-frequency
106          - nvidia,emem-configuration
107
108        additionalProperties: false
109
110    required:
111      - nvidia,ram-code
112
113    additionalProperties: false
114
115required:
116  - compatible
117  - reg
118  - interrupts
119  - clocks
120  - clock-names
121  - "#reset-cells"
122  - "#iommu-cells"
123
124additionalProperties: false
125
126examples:
127  - |
128    memory-controller@7000f000 {
129        compatible = "nvidia,tegra30-mc";
130        reg = <0x7000f000 0x400>;
131        clocks = <&tegra_car 32>;
132        clock-names = "mc";
133
134        interrupts = <0 77 4>;
135
136        #iommu-cells = <1>;
137        #reset-cells = <1>;
138
139        emc-timings-1 {
140            nvidia,ram-code = <1>;
141
142            timing-667000000 {
143                clock-frequency = <667000000>;
144
145                nvidia,emem-configuration = <
146                    0x0000000a /* MC_EMEM_ARB_CFG */
147                    0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
148                    0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
149                    0x00000004 /* MC_EMEM_ARB_TIMING_RP */
150                    0x00000010 /* MC_EMEM_ARB_TIMING_RC */
151                    0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
152                    0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
153                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
154                    0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
155                    0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
156                    0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
157                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
158                    0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
159                    0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
160                    0x08040202 /* MC_EMEM_ARB_DA_TURNS */
161                    0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
162                    0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
163                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
164                >;
165            };
166        };
167    };
168