1*a053b7e5SMarvin Lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a053b7e5SMarvin Lin%YAML 1.2 3*a053b7e5SMarvin Lin--- 4*a053b7e5SMarvin Lin$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml# 5*a053b7e5SMarvin Lin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a053b7e5SMarvin Lin 7*a053b7e5SMarvin Lintitle: Nuvoton NPCM Memory Controller 8*a053b7e5SMarvin Lin 9*a053b7e5SMarvin Linmaintainers: 10*a053b7e5SMarvin Lin - Marvin Lin <kflin@nuvoton.com> 11*a053b7e5SMarvin Lin - Stanley Chu <yschu@nuvoton.com> 12*a053b7e5SMarvin Lin 13*a053b7e5SMarvin Lindescription: | 14*a053b7e5SMarvin Lin The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction 15*a053b7e5SMarvin Lin check). 16*a053b7e5SMarvin Lin 17*a053b7e5SMarvin Lin The memory controller supports single bit error correction, double bit error 18*a053b7e5SMarvin Lin detection (in-line ECC in which a section (1/8th) of the memory device used to 19*a053b7e5SMarvin Lin store data is used for ECC storage). 20*a053b7e5SMarvin Lin 21*a053b7e5SMarvin Lin Note, the bootloader must configure ECC mode for the memory controller. 22*a053b7e5SMarvin Lin 23*a053b7e5SMarvin Linproperties: 24*a053b7e5SMarvin Lin compatible: 25*a053b7e5SMarvin Lin enum: 26*a053b7e5SMarvin Lin - nuvoton,npcm750-memory-controller 27*a053b7e5SMarvin Lin - nuvoton,npcm845-memory-controller 28*a053b7e5SMarvin Lin 29*a053b7e5SMarvin Lin reg: 30*a053b7e5SMarvin Lin maxItems: 1 31*a053b7e5SMarvin Lin 32*a053b7e5SMarvin Lin interrupts: 33*a053b7e5SMarvin Lin maxItems: 1 34*a053b7e5SMarvin Lin 35*a053b7e5SMarvin Linrequired: 36*a053b7e5SMarvin Lin - compatible 37*a053b7e5SMarvin Lin - reg 38*a053b7e5SMarvin Lin - interrupts 39*a053b7e5SMarvin Lin 40*a053b7e5SMarvin LinadditionalProperties: false 41*a053b7e5SMarvin Lin 42*a053b7e5SMarvin Linexamples: 43*a053b7e5SMarvin Lin - | 44*a053b7e5SMarvin Lin #include <dt-bindings/interrupt-controller/arm-gic.h> 45*a053b7e5SMarvin Lin 46*a053b7e5SMarvin Lin mc: memory-controller@f0824000 { 47*a053b7e5SMarvin Lin compatible = "nuvoton,npcm750-memory-controller"; 48*a053b7e5SMarvin Lin reg = <0xf0824000 0x1000>; 49*a053b7e5SMarvin Lin interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 50*a053b7e5SMarvin Lin }; 51