xref: /linux/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml (revision 9dbbc3b9d09d6deba9f3b9e1d5b355032ed46a75) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SMI (Smart Multimedia Interface) Common
9
10maintainers:
11  - Yong Wu <yong.wu@mediatek.com>
12
13description: |
14  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16  MediaTek SMI have two generations of HW architecture, here is the list
17  which generation the SoCs use:
18  generation 1: mt2701 and mt7623.
19  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192.
20
21  There's slight differences between the two SMI, for generation 2, the
22  register which control the iommu port is at each larb's register base. But
23  for generation 1, the register is at smi ao base(smi always on register
24  base). Besides that, the smi async clock should be prepared and enabled for
25  SMI generation 1 to transform the smi clock into emi clock domain, but that is
26  not needed for SMI generation 2.
27
28properties:
29  compatible:
30    oneOf:
31      - enum:
32          - mediatek,mt2701-smi-common
33          - mediatek,mt2712-smi-common
34          - mediatek,mt6779-smi-common
35          - mediatek,mt8167-smi-common
36          - mediatek,mt8173-smi-common
37          - mediatek,mt8183-smi-common
38          - mediatek,mt8192-smi-common
39
40      - description: for mt7623
41        items:
42          - const: mediatek,mt7623-smi-common
43          - const: mediatek,mt2701-smi-common
44
45  reg:
46    maxItems: 1
47
48  power-domains:
49    maxItems: 1
50
51  clocks:
52    description: |
53      apb and smi are mandatory. the async is only for generation 1 smi HW.
54      gals(global async local sync) also is optional, see below.
55    minItems: 2
56    items:
57      - description: apb is Advanced Peripheral Bus clock, It's the clock for
58          setting the register.
59      - description: smi is the clock for transfer data and command.
60      - description: Either asynchronous clock to help transform the smi clock
61          into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
62      - description: gals1 is the path1 clock of gals.
63
64  clock-names:
65    minItems: 2
66    maxItems: 4
67
68required:
69  - compatible
70  - reg
71  - power-domains
72  - clocks
73  - clock-names
74
75allOf:
76  - if:  # only for gen1 HW
77      properties:
78        compatible:
79          contains:
80            enum:
81              - mediatek,mt2701-smi-common
82    then:
83      properties:
84        clock:
85          items:
86            minItems: 3
87            maxItems: 3
88        clock-names:
89          items:
90            - const: apb
91            - const: smi
92            - const: async
93
94  - if:  # for gen2 HW that have gals
95      properties:
96        compatible:
97          enum:
98            - mediatek,mt6779-smi-common
99            - mediatek,mt8183-smi-common
100            - mediatek,mt8192-smi-common
101
102    then:
103      properties:
104        clock:
105          items:
106            minItems: 4
107            maxItems: 4
108        clock-names:
109          items:
110            - const: apb
111            - const: smi
112            - const: gals0
113            - const: gals1
114
115    else:  # for gen2 HW that don't have gals
116      properties:
117        clock:
118          items:
119            minItems: 2
120            maxItems: 2
121        clock-names:
122          items:
123            - const: apb
124            - const: smi
125
126additionalProperties: false
127
128examples:
129  - |+
130    #include <dt-bindings/clock/mt8173-clk.h>
131    #include <dt-bindings/power/mt8173-power.h>
132
133    smi_common: smi@14022000 {
134            compatible = "mediatek,mt8173-smi-common";
135            reg = <0x14022000 0x1000>;
136            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
137            clocks = <&mmsys CLK_MM_SMI_COMMON>,
138                     <&mmsys CLK_MM_SMI_COMMON>;
139            clock-names = "apb", "smi";
140    };
141