1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek Inc. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: SMI (Smart Multimedia Interface) Common 9 10maintainers: 11 - Yong Wu <yong.wu@mediatek.com> 12 13description: | 14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml 15 16 MediaTek SMI have two generations of HW architecture, here is the list 17 which generation the SoCs use: 18 generation 1: mt2701 and mt7623. 19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8189, mt8192 and mt8195. 20 21 There's slight differences between the two SMI, for generation 2, the 22 register which control the iommu port is at each larb's register base. But 23 for generation 1, the register is at smi ao base(smi always on register 24 base). Besides that, the smi async clock should be prepared and enabled for 25 SMI generation 1 to transform the smi clock into emi clock domain, but that is 26 not needed for SMI generation 2. 27 28 The smi-common connects with smi-larb and IOMMU. The maximum inputs number of 29 a smi-common is 8. In SMI generation 2, the engines number may be over 8. 30 In this case, we use a smi-sub-common to merge some larbs. 31 The block diagram something is like: 32 33 IOMMU 34 | | 35 smi-common 36 --------------------------- 37 | | ... 38 larb0 sub-common ... <-max number is 8 39 ---------------- 40 | | ... 41 larb1 larbX ... <-max number is 8 42 43properties: 44 compatible: 45 oneOf: 46 - enum: 47 - mediatek,mt2701-smi-common 48 - mediatek,mt2712-smi-common 49 - mediatek,mt6779-smi-common 50 - mediatek,mt6795-smi-common 51 - mediatek,mt6893-smi-common 52 - mediatek,mt8167-smi-common 53 - mediatek,mt8173-smi-common 54 - mediatek,mt8183-smi-common 55 - mediatek,mt8186-smi-common 56 - mediatek,mt8188-smi-common-vdo 57 - mediatek,mt8188-smi-common-vpp 58 - mediatek,mt8189-smi-common 59 - mediatek,mt8189-smi-sub-common 60 - mediatek,mt8192-smi-common 61 - mediatek,mt8195-smi-common-vdo 62 - mediatek,mt8195-smi-common-vpp 63 - mediatek,mt8195-smi-sub-common 64 - mediatek,mt8365-smi-common 65 66 - description: for mt7623 67 items: 68 - const: mediatek,mt7623-smi-common 69 - const: mediatek,mt2701-smi-common 70 71 reg: 72 maxItems: 1 73 74 power-domains: 75 maxItems: 1 76 77 clocks: 78 description: | 79 apb and smi are mandatory. the async is only for generation 1 smi HW. 80 gals(global async local sync) also is optional, see below. 81 minItems: 2 82 items: 83 - description: apb is Advanced Peripheral Bus clock, It's the clock for 84 setting the register. 85 - description: smi is the clock for transfer data and command. 86 - description: Either asynchronous clock to help transform the smi clock 87 into the emi clock domain on Gen1 h/w, or the path0 clock of gals. 88 - description: gals1 is the path1 clock of gals. 89 90 clock-names: 91 minItems: 2 92 maxItems: 4 93 94 mediatek,smi: 95 $ref: /schemas/types.yaml#/definitions/phandle 96 description: a phandle to the smi-common node above. Only for sub-common. 97 98required: 99 - compatible 100 - reg 101 - power-domains 102 - clocks 103 - clock-names 104 105allOf: 106 - if: # only for gen1 HW 107 properties: 108 compatible: 109 contains: 110 enum: 111 - mediatek,mt2701-smi-common 112 then: 113 properties: 114 clocks: 115 minItems: 3 116 maxItems: 3 117 clock-names: 118 items: 119 - const: apb 120 - const: smi 121 - const: async 122 123 - if: # only for sub common 124 properties: 125 compatible: 126 contains: 127 enum: 128 - mediatek,mt8189-smi-sub-common 129 - mediatek,mt8195-smi-sub-common 130 then: 131 required: 132 - mediatek,smi 133 properties: 134 clocks: 135 minItems: 3 136 maxItems: 3 137 clock-names: 138 items: 139 - const: apb 140 - const: smi 141 - const: gals0 142 else: 143 properties: 144 mediatek,smi: false 145 146 - if: # for gen2 HW that have gals 147 properties: 148 compatible: 149 enum: 150 - mediatek,mt6779-smi-common 151 - mediatek,mt8183-smi-common 152 - mediatek,mt8186-smi-common 153 - mediatek,mt8192-smi-common 154 - mediatek,mt8195-smi-common-vdo 155 - mediatek,mt8195-smi-common-vpp 156 - mediatek,mt8365-smi-common 157 158 then: 159 properties: 160 clocks: 161 minItems: 4 162 maxItems: 4 163 clock-names: 164 items: 165 - const: apb 166 - const: smi 167 - const: gals0 168 - const: gals1 169 170 - if: # for gen2 HW that don't have gals 171 properties: 172 compatible: 173 enum: 174 - mediatek,mt2712-smi-common 175 - mediatek,mt6795-smi-common 176 - mediatek,mt8167-smi-common 177 - mediatek,mt8173-smi-common 178 - mediatek,mt8189-smi-common 179 180 then: 181 properties: 182 clocks: 183 minItems: 2 184 maxItems: 2 185 clock-names: 186 items: 187 - const: apb 188 - const: smi 189 190additionalProperties: false 191 192examples: 193 - |+ 194 #include <dt-bindings/clock/mt8173-clk.h> 195 #include <dt-bindings/power/mt8173-power.h> 196 197 smi_common: smi@14022000 { 198 compatible = "mediatek,mt8173-smi-common"; 199 reg = <0x14022000 0x1000>; 200 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 201 clocks = <&mmsys CLK_MM_SMI_COMMON>, 202 <&mmsys CLK_MM_SMI_COMMON>; 203 clock-names = "apb", "smi"; 204 }; 205