xref: /linux/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml (revision 172cdcaefea5c297fdb3d20b7d5aff60ae4fbce6) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC SROM Controller driver
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12description: |+
13  The SROM controller can be used to attach external peripherals. In this case
14  extra properties, describing the bus behind it, should be specified.
15
16properties:
17  compatible:
18    items:
19      - const: samsung,exynos4210-srom
20
21  reg:
22    maxItems: 1
23
24  "#address-cells":
25    const: 2
26
27  "#size-cells":
28    const: 1
29
30  ranges:
31    minItems: 1
32    maxItems: 4
33    description: |
34      Reflects the memory layout with four integer values per bank. Format:
35      <bank-number> 0 <parent address of bank> <size>
36      Up to four banks are supported.
37
38patternProperties:
39  "^.*@[0-3],[a-f0-9]+$":
40    type: object
41    description:
42      The actual device nodes should be added as subnodes to the SROMc node.
43      These subnodes, in addition to regular device specification, should
44      contain the following properties, describing configuration
45      of the relevant SROM bank.
46
47    properties:
48      reg:
49        description:
50          Bank number, base address (relative to start of the bank) and size
51          of the memory mapped for the device. Note that base address will be
52          typically 0 as this is the start of the bank.
53        maxItems: 1
54
55      reg-io-width:
56        enum: [1, 2]
57        description:
58          Data width in bytes (1 or 2). If omitted, default of 1 is used.
59
60      samsung,srom-page-mode:
61        description:
62          If page mode is set, 4 data page mode will be configured,
63          else normal (1 data) page mode will be set.
64        type: boolean
65
66      samsung,srom-timing:
67        $ref: /schemas/types.yaml#/definitions/uint32-array
68        items:
69          minItems: 6
70          maxItems: 6
71        description: |
72          Array of 6 integers, specifying bank timings in the following order:
73          Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
74          Each value is specified in cycles and has the following meaning
75          and valid range:
76          Tacp: Page mode access cycle at Page mode (0 - 15)
77          Tcah: Address holding time after CSn (0 - 15)
78          Tcoh: Chip selection hold on OEn (0 - 15)
79          Tacc: Access cycle (0 - 31, the actual time is N + 1)
80          Tcos: Chip selection set-up before OEn (0 - 15)
81          Tacs: Address set-up before CSn (0 - 15)
82
83    required:
84      - reg
85      - samsung,srom-timing
86
87required:
88  - compatible
89  - reg
90
91additionalProperties: false
92
93examples:
94  - |
95    // Example: basic definition, no banks are configured
96    memory-controller@12560000 {
97        compatible = "samsung,exynos4210-srom";
98        reg = <0x12560000 0x14>;
99    };
100
101  - |
102    // Example: SROMc with SMSC911x ethernet chip on bank 3
103    memory-controller@12570000 {
104        #address-cells = <2>;
105        #size-cells = <1>;
106        ranges = <0 0 0x04000000 0x20000   // Bank0
107                  1 0 0x05000000 0x20000   // Bank1
108                  2 0 0x06000000 0x20000   // Bank2
109                  3 0 0x07000000 0x20000>; // Bank3
110
111        compatible = "samsung,exynos4210-srom";
112        reg = <0x12570000 0x14>;
113
114        ethernet@3,0 {
115            compatible = "smsc,lan9115";
116            reg = <3 0 0x10000>;     // Bank 3, offset = 0
117            phy-mode = "mii";
118            interrupt-parent = <&gpx0>;
119            interrupts = <5 8>;
120            reg-io-width = <2>;
121            smsc,irq-push-pull;
122            smsc,force-internal-phy;
123
124            samsung,srom-page-mode;
125            samsung,srom-timing = <9 12 1 9 1 1>;
126        };
127    };
128