xref: /linux/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml (revision 24bce201d79807b668bf9d9e0aca801c5c0d5f78) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - samsung,K3QF2F20DB
17      - const: jedec,lpddr3
18
19  '#address-cells':
20    const: 1
21    deprecated: true
22
23  density:
24    $ref: /schemas/types.yaml#/definitions/uint32
25    description: |
26      Density in megabits of SDRAM chip.
27    enum:
28      - 4096
29      - 8192
30      - 16384
31      - 32768
32
33  io-width:
34    $ref: /schemas/types.yaml#/definitions/uint32
35    description: |
36      IO bus width in bits of SDRAM chip.
37    enum:
38      - 32
39      - 16
40
41  manufacturer-id:
42    $ref: /schemas/types.yaml#/definitions/uint32
43    description: |
44      Manufacturer ID value read from Mode Register 5.  The property is
45      deprecated, manufacturer should be derived from the compatible.
46    deprecated: true
47
48  revision-id:
49    $ref: /schemas/types.yaml#/definitions/uint32-array
50    minItems: 2
51    maxItems: 2
52    items:
53      maximum: 255
54    description: |
55      Revision value of SDRAM chip read from Mode Registers 6 and 7.
56
57  '#size-cells':
58    const: 0
59    deprecated: true
60
61  tCKE-min-tck:
62    $ref: /schemas/types.yaml#/definitions/uint32
63    maximum: 15
64    description: |
65      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
66      of clock cycles.
67
68  tCKESR-min-tck:
69    $ref: /schemas/types.yaml#/definitions/uint32
70    maximum: 15
71    description: |
72      CKE minimum pulse width during SELF REFRESH (low pulse width during
73      SELF REFRESH) in terms of number of clock cycles.
74
75  tDQSCK-min-tck:
76    $ref: /schemas/types.yaml#/definitions/uint32
77    maximum: 15
78    description: |
79      DQS output data access time from CK_t/CK_c in terms of number of clock
80      cycles.
81
82  tFAW-min-tck:
83    $ref: /schemas/types.yaml#/definitions/uint32
84    maximum: 63
85    description: |
86      Four-bank activate window in terms of number of clock cycles.
87
88  tMRD-min-tck:
89    $ref: /schemas/types.yaml#/definitions/uint32
90    maximum: 15
91    description: |
92      Mode register set command delay in terms of number of clock cycles.
93
94  tR2R-C2C-min-tck:
95    $ref: /schemas/types.yaml#/definitions/uint32
96    enum: [0, 1]
97    description: |
98      Additional READ-to-READ delay in chip-to-chip cases in terms of number
99      of clock cycles.
100
101  tRAS-min-tck:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    maximum: 63
104    description: |
105      Row active time in terms of number of clock cycles.
106
107  tRC-min-tck:
108    $ref: /schemas/types.yaml#/definitions/uint32
109    maximum: 63
110    description: |
111      ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
112
113  tRCD-min-tck:
114    $ref: /schemas/types.yaml#/definitions/uint32
115    maximum: 15
116    description: |
117      RAS-to-CAS delay in terms of number of clock cycles.
118
119  tRFC-min-tck:
120    $ref: /schemas/types.yaml#/definitions/uint32
121    maximum: 255
122    description: |
123      Refresh Cycle time in terms of number of clock cycles.
124
125  tRL-min-tck:
126    $ref: /schemas/types.yaml#/definitions/uint32
127    maximum: 15
128    description: |
129     READ data latency in terms of number of clock cycles.
130
131  tRPab-min-tck:
132    $ref: /schemas/types.yaml#/definitions/uint32
133    maximum: 15
134    description: |
135      Row precharge time (all banks) in terms of number of clock cycles.
136
137  tRPpb-min-tck:
138    $ref: /schemas/types.yaml#/definitions/uint32
139    maximum: 15
140    description: |
141      Row precharge time (single banks) in terms of number of clock cycles.
142
143  tRRD-min-tck:
144    $ref: /schemas/types.yaml#/definitions/uint32
145    maximum: 15
146    description: |
147      Active bank A to active bank B in terms of number of clock cycles.
148
149  tRTP-min-tck:
150    $ref: /schemas/types.yaml#/definitions/uint32
151    maximum: 15
152    description: |
153      Internal READ to PRECHARGE command delay in terms of number of clock
154      cycles.
155
156  tW2W-C2C-min-tck:
157    $ref: /schemas/types.yaml#/definitions/uint32
158    enum: [0, 1]
159    description: |
160      Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
161      of clock cycles.
162
163  tWL-min-tck:
164    $ref: /schemas/types.yaml#/definitions/uint32
165    maximum: 15
166    description: |
167      WRITE data latency in terms of number of clock cycles.
168
169  tWR-min-tck:
170    $ref: /schemas/types.yaml#/definitions/uint32
171    maximum: 15
172    description: |
173      WRITE recovery time in terms of number of clock cycles.
174
175  tWTR-min-tck:
176    $ref: /schemas/types.yaml#/definitions/uint32
177    maximum: 15
178    description: |
179      Internal WRITE-to-READ command delay in terms of number of clock cycles.
180
181  tXP-min-tck:
182    $ref: /schemas/types.yaml#/definitions/uint32
183    maximum: 255
184    description: |
185      Exit power-down to next valid command delay in terms of number of clock
186      cycles.
187
188  tXSR-min-tck:
189    $ref: /schemas/types.yaml#/definitions/uint32
190    maximum: 1023
191    description: |
192      SELF REFRESH exit to next valid command delay in terms of number of clock
193      cycles.
194
195patternProperties:
196  "^timings((-[0-9])+|(@[0-9a-f]+))?$":
197    $ref: jedec,lpddr3-timings.yaml
198    description: |
199      The lpddr3 node may have one or more child nodes with timings.
200      Each timing node provides AC timing parameters of the device for a given
201      speed-bin. The user may provide the timings for as many speed-bins as is
202      required.
203
204required:
205  - compatible
206  - density
207  - io-width
208
209additionalProperties: false
210
211examples:
212  - |
213    lpddr3 {
214        compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
215        density = <16384>;
216        io-width = <32>;
217
218        tCKE-min-tck = <2>;
219        tCKESR-min-tck = <2>;
220        tDQSCK-min-tck = <5>;
221        tFAW-min-tck = <5>;
222        tMRD-min-tck = <5>;
223        tR2R-C2C-min-tck = <0>;
224        tRAS-min-tck = <5>;
225        tRC-min-tck = <6>;
226        tRCD-min-tck = <3>;
227        tRFC-min-tck = <17>;
228        tRL-min-tck = <14>;
229        tRPab-min-tck = <2>;
230        tRPpb-min-tck = <2>;
231        tRRD-min-tck = <2>;
232        tRTP-min-tck = <2>;
233        tW2W-C2C-min-tck = <0>;
234        tWL-min-tck = <8>;
235        tWR-min-tck = <7>;
236        tWTR-min-tck = <2>;
237        tXP-min-tck = <2>;
238        tXSR-min-tck = <12>;
239
240        timings {
241            compatible = "jedec,lpddr3-timings";
242            max-freq = <800000000>;
243            min-freq = <100000000>;
244            tCKE = <3750>;
245            tCKESR = <3750>;
246            tFAW = <25000>;
247            tMRD = <7000>;
248            tR2R-C2C = <0>;
249            tRAS = <23000>;
250            tRC = <33750>;
251            tRCD = <10000>;
252            tRFC = <65000>;
253            tRPab = <12000>;
254            tRPpb = <12000>;
255            tRRD = <6000>;
256            tRTP = <3750>;
257            tW2W-C2C = <0>;
258            tWR = <7500>;
259            tWTR = <3750>;
260            tXP = <3750>;
261            tXSR = <70000>;
262        };
263    };
264