1*9e17f71eSDmitry Osipenko# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*9e17f71eSDmitry Osipenko%YAML 1.2 3*9e17f71eSDmitry Osipenko--- 4*9e17f71eSDmitry Osipenko$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml# 5*9e17f71eSDmitry Osipenko$schema: http://devicetree.org/meta-schemas/core.yaml# 6*9e17f71eSDmitry Osipenko 7*9e17f71eSDmitry Osipenkotitle: LPDDR2 SDRAM compliant to JEDEC JESD209-2 8*9e17f71eSDmitry Osipenko 9*9e17f71eSDmitry Osipenkomaintainers: 10*9e17f71eSDmitry Osipenko - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11*9e17f71eSDmitry Osipenko 12*9e17f71eSDmitry Osipenkoproperties: 13*9e17f71eSDmitry Osipenko compatible: 14*9e17f71eSDmitry Osipenko oneOf: 15*9e17f71eSDmitry Osipenko - items: 16*9e17f71eSDmitry Osipenko - enum: 17*9e17f71eSDmitry Osipenko - elpida,ECB240ABACN 18*9e17f71eSDmitry Osipenko - enum: 19*9e17f71eSDmitry Osipenko - jedec,lpddr2-s4 20*9e17f71eSDmitry Osipenko - items: 21*9e17f71eSDmitry Osipenko - enum: 22*9e17f71eSDmitry Osipenko - jedec,lpddr2-s2 23*9e17f71eSDmitry Osipenko - items: 24*9e17f71eSDmitry Osipenko - enum: 25*9e17f71eSDmitry Osipenko - jedec,lpddr2-nvm 26*9e17f71eSDmitry Osipenko 27*9e17f71eSDmitry Osipenko density: 28*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 29*9e17f71eSDmitry Osipenko description: | 30*9e17f71eSDmitry Osipenko Density in megabits of SDRAM chip. Obtained from device datasheet. 31*9e17f71eSDmitry Osipenko enum: 32*9e17f71eSDmitry Osipenko - 64 33*9e17f71eSDmitry Osipenko - 128 34*9e17f71eSDmitry Osipenko - 256 35*9e17f71eSDmitry Osipenko - 512 36*9e17f71eSDmitry Osipenko - 1024 37*9e17f71eSDmitry Osipenko - 2048 38*9e17f71eSDmitry Osipenko - 4096 39*9e17f71eSDmitry Osipenko - 8192 40*9e17f71eSDmitry Osipenko - 16384 41*9e17f71eSDmitry Osipenko - 32768 42*9e17f71eSDmitry Osipenko 43*9e17f71eSDmitry Osipenko io-width: 44*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 45*9e17f71eSDmitry Osipenko description: | 46*9e17f71eSDmitry Osipenko IO bus width in bits of SDRAM chip. Obtained from device datasheet. 47*9e17f71eSDmitry Osipenko enum: 48*9e17f71eSDmitry Osipenko - 32 49*9e17f71eSDmitry Osipenko - 16 50*9e17f71eSDmitry Osipenko - 8 51*9e17f71eSDmitry Osipenko 52*9e17f71eSDmitry Osipenko tRRD-min-tck: 53*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 54*9e17f71eSDmitry Osipenko maximum: 16 55*9e17f71eSDmitry Osipenko description: | 56*9e17f71eSDmitry Osipenko Active bank a to active bank b in terms of number of clock cycles. 57*9e17f71eSDmitry Osipenko Obtained from device datasheet. 58*9e17f71eSDmitry Osipenko 59*9e17f71eSDmitry Osipenko tWTR-min-tck: 60*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 61*9e17f71eSDmitry Osipenko maximum: 16 62*9e17f71eSDmitry Osipenko description: | 63*9e17f71eSDmitry Osipenko Internal WRITE-to-READ command delay in terms of number of clock cycles. 64*9e17f71eSDmitry Osipenko Obtained from device datasheet. 65*9e17f71eSDmitry Osipenko 66*9e17f71eSDmitry Osipenko tXP-min-tck: 67*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 68*9e17f71eSDmitry Osipenko maximum: 16 69*9e17f71eSDmitry Osipenko description: | 70*9e17f71eSDmitry Osipenko Exit power-down to next valid command delay in terms of number of clock 71*9e17f71eSDmitry Osipenko cycles. Obtained from device datasheet. 72*9e17f71eSDmitry Osipenko 73*9e17f71eSDmitry Osipenko tRTP-min-tck: 74*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 75*9e17f71eSDmitry Osipenko maximum: 16 76*9e17f71eSDmitry Osipenko description: | 77*9e17f71eSDmitry Osipenko Internal READ to PRECHARGE command delay in terms of number of clock 78*9e17f71eSDmitry Osipenko cycles. Obtained from device datasheet. 79*9e17f71eSDmitry Osipenko 80*9e17f71eSDmitry Osipenko tCKE-min-tck: 81*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 82*9e17f71eSDmitry Osipenko maximum: 16 83*9e17f71eSDmitry Osipenko description: | 84*9e17f71eSDmitry Osipenko CKE minimum pulse width (HIGH and LOW pulse width) in terms of number 85*9e17f71eSDmitry Osipenko of clock cycles. Obtained from device datasheet. 86*9e17f71eSDmitry Osipenko 87*9e17f71eSDmitry Osipenko tRPab-min-tck: 88*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 89*9e17f71eSDmitry Osipenko maximum: 16 90*9e17f71eSDmitry Osipenko description: | 91*9e17f71eSDmitry Osipenko Row precharge time (all banks) in terms of number of clock cycles. 92*9e17f71eSDmitry Osipenko Obtained from device datasheet. 93*9e17f71eSDmitry Osipenko 94*9e17f71eSDmitry Osipenko tRCD-min-tck: 95*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 96*9e17f71eSDmitry Osipenko maximum: 16 97*9e17f71eSDmitry Osipenko description: | 98*9e17f71eSDmitry Osipenko RAS-to-CAS delay in terms of number of clock cycles. Obtained from 99*9e17f71eSDmitry Osipenko device datasheet. 100*9e17f71eSDmitry Osipenko 101*9e17f71eSDmitry Osipenko tWR-min-tck: 102*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 103*9e17f71eSDmitry Osipenko maximum: 16 104*9e17f71eSDmitry Osipenko description: | 105*9e17f71eSDmitry Osipenko WRITE recovery time in terms of number of clock cycles. Obtained from 106*9e17f71eSDmitry Osipenko device datasheet. 107*9e17f71eSDmitry Osipenko 108*9e17f71eSDmitry Osipenko tRASmin-min-tck: 109*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 110*9e17f71eSDmitry Osipenko maximum: 16 111*9e17f71eSDmitry Osipenko description: | 112*9e17f71eSDmitry Osipenko Row active time in terms of number of clock cycles. Obtained from device 113*9e17f71eSDmitry Osipenko datasheet. 114*9e17f71eSDmitry Osipenko 115*9e17f71eSDmitry Osipenko tCKESR-min-tck: 116*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 117*9e17f71eSDmitry Osipenko maximum: 16 118*9e17f71eSDmitry Osipenko description: | 119*9e17f71eSDmitry Osipenko CKE minimum pulse width during SELF REFRESH (low pulse width during 120*9e17f71eSDmitry Osipenko SELF REFRESH) in terms of number of clock cycles. Obtained from device 121*9e17f71eSDmitry Osipenko datasheet. 122*9e17f71eSDmitry Osipenko 123*9e17f71eSDmitry Osipenko tFAW-min-tck: 124*9e17f71eSDmitry Osipenko $ref: /schemas/types.yaml#/definitions/uint32 125*9e17f71eSDmitry Osipenko maximum: 16 126*9e17f71eSDmitry Osipenko description: | 127*9e17f71eSDmitry Osipenko Four-bank activate window in terms of number of clock cycles. Obtained 128*9e17f71eSDmitry Osipenko from device datasheet. 129*9e17f71eSDmitry Osipenko 130*9e17f71eSDmitry OsipenkopatternProperties: 131*9e17f71eSDmitry Osipenko "^lpddr2-timings": 132*9e17f71eSDmitry Osipenko type: object 133*9e17f71eSDmitry Osipenko description: | 134*9e17f71eSDmitry Osipenko The lpddr2 node may have one or more child nodes of type "lpddr2-timings". 135*9e17f71eSDmitry Osipenko "lpddr2-timings" provides AC timing parameters of the device for 136*9e17f71eSDmitry Osipenko a given speed-bin. The user may provide the timings for as many 137*9e17f71eSDmitry Osipenko speed-bins as is required. Please see Documentation/devicetree/ 138*9e17f71eSDmitry Osipenko bindings/memory-controllers/ddr/lpddr2-timings.txt for more information 139*9e17f71eSDmitry Osipenko on "lpddr2-timings". 140*9e17f71eSDmitry Osipenko 141*9e17f71eSDmitry Osipenkorequired: 142*9e17f71eSDmitry Osipenko - compatible 143*9e17f71eSDmitry Osipenko - density 144*9e17f71eSDmitry Osipenko - io-width 145*9e17f71eSDmitry Osipenko 146*9e17f71eSDmitry OsipenkoadditionalProperties: false 147*9e17f71eSDmitry Osipenko 148*9e17f71eSDmitry Osipenkoexamples: 149*9e17f71eSDmitry Osipenko - | 150*9e17f71eSDmitry Osipenko elpida_ECB240ABACN: lpddr2 { 151*9e17f71eSDmitry Osipenko compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4"; 152*9e17f71eSDmitry Osipenko density = <2048>; 153*9e17f71eSDmitry Osipenko io-width = <32>; 154*9e17f71eSDmitry Osipenko 155*9e17f71eSDmitry Osipenko tRPab-min-tck = <3>; 156*9e17f71eSDmitry Osipenko tRCD-min-tck = <3>; 157*9e17f71eSDmitry Osipenko tWR-min-tck = <3>; 158*9e17f71eSDmitry Osipenko tRASmin-min-tck = <3>; 159*9e17f71eSDmitry Osipenko tRRD-min-tck = <2>; 160*9e17f71eSDmitry Osipenko tWTR-min-tck = <2>; 161*9e17f71eSDmitry Osipenko tXP-min-tck = <2>; 162*9e17f71eSDmitry Osipenko tRTP-min-tck = <2>; 163*9e17f71eSDmitry Osipenko tCKE-min-tck = <3>; 164*9e17f71eSDmitry Osipenko tCKESR-min-tck = <3>; 165*9e17f71eSDmitry Osipenko tFAW-min-tck = <8>; 166*9e17f71eSDmitry Osipenko 167*9e17f71eSDmitry Osipenko timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 { 168*9e17f71eSDmitry Osipenko compatible = "jedec,lpddr2-timings"; 169*9e17f71eSDmitry Osipenko min-freq = <10000000>; 170*9e17f71eSDmitry Osipenko max-freq = <400000000>; 171*9e17f71eSDmitry Osipenko tRPab = <21000>; 172*9e17f71eSDmitry Osipenko tRCD = <18000>; 173*9e17f71eSDmitry Osipenko tWR = <15000>; 174*9e17f71eSDmitry Osipenko tRAS-min = <42000>; 175*9e17f71eSDmitry Osipenko tRRD = <10000>; 176*9e17f71eSDmitry Osipenko tWTR = <7500>; 177*9e17f71eSDmitry Osipenko tXP = <7500>; 178*9e17f71eSDmitry Osipenko tRTP = <7500>; 179*9e17f71eSDmitry Osipenko tCKESR = <15000>; 180*9e17f71eSDmitry Osipenko tDQSCK-max = <5500>; 181*9e17f71eSDmitry Osipenko tFAW = <50000>; 182*9e17f71eSDmitry Osipenko tZQCS = <90000>; 183*9e17f71eSDmitry Osipenko tZQCL = <360000>; 184*9e17f71eSDmitry Osipenko tZQinit = <1000000>; 185*9e17f71eSDmitry Osipenko tRAS-max-ns = <70000>; 186*9e17f71eSDmitry Osipenko }; 187*9e17f71eSDmitry Osipenko 188*9e17f71eSDmitry Osipenko timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 { 189*9e17f71eSDmitry Osipenko compatible = "jedec,lpddr2-timings"; 190*9e17f71eSDmitry Osipenko min-freq = <10000000>; 191*9e17f71eSDmitry Osipenko max-freq = <200000000>; 192*9e17f71eSDmitry Osipenko tRPab = <21000>; 193*9e17f71eSDmitry Osipenko tRCD = <18000>; 194*9e17f71eSDmitry Osipenko tWR = <15000>; 195*9e17f71eSDmitry Osipenko tRAS-min = <42000>; 196*9e17f71eSDmitry Osipenko tRRD = <10000>; 197*9e17f71eSDmitry Osipenko tWTR = <10000>; 198*9e17f71eSDmitry Osipenko tXP = <7500>; 199*9e17f71eSDmitry Osipenko tRTP = <7500>; 200*9e17f71eSDmitry Osipenko tCKESR = <15000>; 201*9e17f71eSDmitry Osipenko tDQSCK-max = <5500>; 202*9e17f71eSDmitry Osipenko tFAW = <50000>; 203*9e17f71eSDmitry Osipenko tZQCS = <90000>; 204*9e17f71eSDmitry Osipenko tZQCL = <360000>; 205*9e17f71eSDmitry Osipenko tZQinit = <1000000>; 206*9e17f71eSDmitry Osipenko tRAS-max-ns = <70000>; 207*9e17f71eSDmitry Osipenko }; 208*9e17f71eSDmitry Osipenko }; 209