1* Device tree bindings for ARM PL172 MultiPort Memory Controller 2 3Required properties: 4 5- compatible: "arm,pl172", "arm,primecell" 6 7- reg: Must contains offset/length value for controller. 8 9- #address-cells: Must be 2. The partition number has to be encoded in the 10 first address cell and it may accept values 0..N-1 11 (N - total number of partitions). The second cell is the 12 offset into the partition. 13 14- #size-cells: Must be set to 1. 15 16- ranges: Must contain one or more chip select memory regions. 17 18- clocks: Must contain references to controller clocks. 19 20- clock-names: Must contain "mpmcclk" and "apb_pclk". 21 22- clock-ranges: Empty property indicating that child nodes can inherit 23 named clocks. Required only if clock tree data present 24 in device tree. 25 See clock-bindings.txt 26 27Child chip-select (cs) nodes contain the memory devices nodes connected to 28such as NOR (e.g. cfi-flash) and NAND. 29 30Required child cs node properties: 31 32- #address-cells: Must be 2. 33 34- #size-cells: Must be 1. 35 36- ranges: Empty property indicating that child nodes can inherit 37 memory layout. 38 39- clock-ranges: Empty property indicating that child nodes can inherit 40 named clocks. Required only if clock tree data present 41 in device tree. 42 43- mpmc,cs: Chip select number. Indicates to the pl0172 driver 44 which chipselect is used for accessing the memory. 45 46- mpmc,memory-width: Width of the chip select memory. Must be equal to 47 either 8, 16 or 32. 48 49Optional child cs node config properties: 50 51- mpmc,async-page-mode: Enable asynchronous page mode. 52 53- mpmc,cs-active-high: Set chip select polarity to active high. 54 55- mpmc,byte-lane-low: Set byte lane state to low. 56 57- mpmc,extended-wait: Enable extended wait. 58 59- mpmc,buffer-enable: Enable write buffer. 60 61- mpmc,write-protect: Enable write protect. 62 63Optional child cs node timing properties: 64 65- mpmc,write-enable-delay: Delay from chip select assertion to write 66 enable (WE signal) in nano seconds. 67 68- mpmc,output-enable-delay: Delay from chip select assertion to output 69 enable (OE signal) in nano seconds. 70 71- mpmc,write-access-delay: Delay from chip select assertion to write 72 access in nano seconds. 73 74- mpmc,read-access-delay: Delay from chip select assertion to read 75 access in nano seconds. 76 77- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential 78 accesses in nano seconds. 79 80- mpmc,turn-round-delay: Delay between access to memory banks in nano 81 seconds. 82 83If any of the above timing parameters are absent, current parameter value will 84be taken from the corresponding HW reg. 85 86Example for pl172 with nor flash on chip select 0 shown below. 87 88emc: memory-controller@40005000 { 89 compatible = "arm,pl172", "arm,primecell"; 90 reg = <0x40005000 0x1000>; 91 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; 92 clock-names = "mpmcclk", "apb_pclk"; 93 #address-cells = <2>; 94 #size-cells = <1>; 95 ranges = <0 0 0x1c000000 0x1000000 96 1 0 0x1d000000 0x1000000 97 2 0 0x1e000000 0x1000000 98 3 0 0x1f000000 0x1000000>; 99 100 cs0 { 101 #address-cells = <2>; 102 #size-cells = <1>; 103 ranges; 104 105 mpmc,cs = <0>; 106 mpmc,memory-width = <16>; 107 mpmc,byte-lane-low; 108 mpmc,write-enable-delay = <0>; 109 mpmc,output-enable-delay = <0>; 110 mpmc,read-enable-delay = <70>; 111 mpmc,page-mode-read-delay = <70>; 112 113 flash@0,0 { 114 compatible = "sst,sst39vf320", "cfi-flash"; 115 reg = <0 0 0x400000>; 116 bank-width = <2>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 partition@0 { 120 label = "data"; 121 reg = <0 0x400000>; 122 }; 123 }; 124 }; 125}; 126