xref: /linux/Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml (revision d42b1c47570eb2ed818dc3fe94b2678124af109d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm PL35x Series Static Memory Controller (SMC)
8
9maintainers:
10  - Miquel Raynal <miquel.raynal@bootlin.com>
11  - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
12
13description: |
14  The PL35x Static Memory Controller is a bus where you can connect two kinds
15  of memory interfaces, which are NAND and memory mapped interfaces (such as
16  SRAM or NOR) depending on the specific configuration.
17
18  The TRM is available here:
19  https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
20
21# We need a select here so we don't match all nodes with 'arm,primecell'
22select:
23  properties:
24    compatible:
25      contains:
26        enum:
27          - arm,pl353-smc-r2p1
28          - arm,pl354
29  required:
30    - compatible
31
32properties:
33  $nodename:
34    pattern: "^memory-controller@[0-9a-f]+$"
35
36  compatible:
37    items:
38      - enum:
39          - arm,pl353-smc-r2p1
40          - arm,pl354
41      - const: arm,primecell
42
43  "#address-cells":
44    const: 2
45
46  "#size-cells":
47    const: 1
48
49  reg:
50    items:
51      - description:
52          Configuration registers for the host and sub-controllers.
53          The three chip select regions are defined in 'ranges'.
54
55  clocks:
56    minItems: 1
57    maxItems: 2
58
59  clock-names:
60    minItems: 1
61    maxItems: 2
62
63  ranges:
64    minItems: 1
65    maxItems: 8
66
67  interrupts:
68    minItems: 1
69    items:
70      - description: Combined or Memory interface 0 IRQ
71      - description: Memory interface 1 IRQ
72
73patternProperties:
74  "@[0-7],[a-f0-9]+$":
75    type: object
76    additionalProperties: true
77    description: |
78      The child device node represents the controller connected to the SMC
79      bus. The controller can be a NAND controller or a pair of any memory
80      mapped controllers such as NOR and SRAM controllers.
81
82    properties:
83      compatible:
84        description:
85          Compatible of memory controller.
86
87      reg:
88        items:
89          - items:
90              - description: |
91                  Chip-select ID, as in the parent range property.
92                minimum: 0
93                maximum: 7
94              - description: |
95                  Offset of the memory region requested by the device.
96              - description: |
97                  Length of the memory region requested by the device.
98
99    required:
100      - compatible
101      - reg
102
103required:
104  - compatible
105  - reg
106  - clock-names
107  - clocks
108
109additionalProperties: false
110
111allOf:
112  - if:
113      properties:
114        compatible:
115          contains:
116            const: arm,pl354
117    then:
118      properties:
119        clocks:
120          # According to TRM, really should be 3 clocks
121          maxItems: 1
122
123        clock-names:
124          const: apb_pclk
125
126    else:
127      properties:
128        clocks:
129          items:
130            - description: clock for the memory device bus
131            - description: main clock of the SMC
132
133        clock-names:
134          items:
135            - const: memclk
136            - const: apb_pclk
137
138examples:
139  - |
140    smcc: memory-controller@e000e000 {
141      compatible = "arm,pl353-smc-r2p1", "arm,primecell";
142      reg = <0xe000e000 0x0001000>;
143      clock-names = "memclk", "apb_pclk";
144      clocks = <&clkc 11>, <&clkc 44>;
145      ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
146                0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
147                0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
148      #address-cells = <2>;
149      #size-cells = <1>;
150
151      nfc0: nand-controller@0,0 {
152        compatible = "arm,pl353-nand-r2p1";
153        reg = <0 0 0x1000000>;
154        #address-cells = <1>;
155        #size-cells = <0>;
156      };
157    };
158