1Common bindings for video receiver and transmitter interfaces 2 3General concept 4--------------- 5 6Video data pipelines usually consist of external devices, e.g. camera sensors, 7controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including 8video DMA engines and video data processors. 9 10SoC internal blocks are described by DT nodes, placed similarly to other SoC 11blocks. External devices are represented as child nodes of their respective 12bus controller nodes, e.g. I2C. 13 14Data interfaces on all video devices are described by their child 'port' nodes. 15Configuration of a port depends on other devices participating in the data 16transfer and is described by 'endpoint' subnodes. 17 18device { 19 ... 20 ports { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 port@0 { 25 ... 26 endpoint@0 { ... }; 27 endpoint@1 { ... }; 28 }; 29 port@1 { ... }; 30 }; 31}; 32 33If a port can be configured to work with more than one remote device on the same 34bus, an 'endpoint' child node must be provided for each of them. If more than 35one port is present in a device node or there is more than one endpoint at a 36port, or port node needs to be associated with a selected hardware interface, 37a common scheme using '#address-cells', '#size-cells' and 'reg' properties is 38used. 39 40All 'port' nodes can be grouped under optional 'ports' node, which allows to 41specify #address-cells, #size-cells properties independently for the 'port' 42and 'endpoint' nodes and any child device nodes a device might have. 43 44Two 'endpoint' nodes are linked with each other through their 'remote-endpoint' 45phandles. An endpoint subnode of a device contains all properties needed for 46configuration of this device for data exchange with other device. In most 47cases properties at the peer 'endpoint' nodes will be identical, however they 48might need to be different when there is any signal modifications on the bus 49between two devices, e.g. there are logic signal inverters on the lines. 50 51It is allowed for multiple endpoints at a port to be active simultaneously, 52where supported by a device. For example, in case where a data interface of 53a device is partitioned into multiple data busses, e.g. 16-bit input port 54divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width 55and data-shift properties can be used to assign physical data lines to each 56endpoint node (logical bus). 57 58 59Required properties 60------------------- 61 62If there is more than one 'port' or more than one 'endpoint' node or 'reg' 63property is present in port and/or endpoint nodes the following properties 64are required in a relevant parent node: 65 66 - #address-cells : number of cells required to define port/endpoint 67 identifier, should be 1. 68 - #size-cells : should be zero. 69 70Optional endpoint properties 71---------------------------- 72 73- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node. 74- slave-mode: a boolean property indicating that the link is run in slave mode. 75 The default when this property is not specified is master mode. In the slave 76 mode horizontal and vertical synchronization signals are provided to the 77 slave device (data source) by the master device (data sink). In the master 78 mode the data source device is also the source of the synchronization signals. 79- bus-width: number of data lines actively used, valid for the parallel busses. 80- data-shift: on the parallel data busses, if bus-width is used to specify the 81 number of data lines, data-shift can be used to specify which data lines are 82 used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used. 83- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. 84- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. 85 Note, that if HSYNC and VSYNC polarities are not specified, embedded 86 synchronization may be required, where supported. 87- data-active: similar to HSYNC and VSYNC, specifies data line polarity. 88- field-even-active: field signal level during the even field data transmission. 89- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock 90 signal. 91- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for 92 LOW/HIGH respectively. 93- data-lanes: an array of physical data lane indexes. Position of an entry 94 determines the logical lane number, while the value of an entry indicates 95 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have 96 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. 97 This property is valid for serial busses only (e.g. MIPI CSI-2). 98- clock-lanes: an array of physical clock lane indexes. Position of an entry 99 determines the logical lane number, while the value of an entry indicates 100 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", 101 which places the clock lane on hardware lane 0. This property is valid for 102 serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this 103 array contains only one entry. 104- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous 105 clock mode. 106 107 108Example 109------- 110 111The example snippet below describes two data pipelines. ov772x and imx074 are 112camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively. 113Both sensors are on the I2C control bus corresponding to the i2c0 controller 114node. ov772x sensor is linked directly to the ceu0 video host interface. 115imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a 116(single) DMA engine writing captured data to memory. ceu0 node has a single 117'port' node which may indicate that at any time only one of the following data 118pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. 119 120 ceu0: ceu@0xfe910000 { 121 compatible = "renesas,sh-mobile-ceu"; 122 reg = <0xfe910000 0xa0>; 123 interrupts = <0x880>; 124 125 mclk: master_clock { 126 compatible = "renesas,ceu-clock"; 127 #clock-cells = <1>; 128 clock-frequency = <50000000>; /* Max clock frequency */ 129 clock-output-names = "mclk"; 130 }; 131 132 port { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 /* Parallel bus endpoint */ 137 ceu0_1: endpoint@1 { 138 reg = <1>; /* Local endpoint # */ 139 remote = <&ov772x_1_1>; /* Remote phandle */ 140 bus-width = <8>; /* Used data lines */ 141 data-shift = <2>; /* Lines 9:2 are used */ 142 143 /* If hsync-active/vsync-active are missing, 144 embedded BT.656 sync is used */ 145 hsync-active = <0>; /* Active low */ 146 vsync-active = <0>; /* Active low */ 147 data-active = <1>; /* Active high */ 148 pclk-sample = <1>; /* Rising */ 149 }; 150 151 /* MIPI CSI-2 bus endpoint */ 152 ceu0_0: endpoint@0 { 153 reg = <0>; 154 remote = <&csi2_2>; 155 }; 156 }; 157 }; 158 159 i2c0: i2c@0xfff20000 { 160 ... 161 ov772x_1: camera@0x21 { 162 compatible = "omnivision,ov772x"; 163 reg = <0x21>; 164 vddio-supply = <®ulator1>; 165 vddcore-supply = <®ulator2>; 166 167 clock-frequency = <20000000>; 168 clocks = <&mclk 0>; 169 clock-names = "xclk"; 170 171 port { 172 /* With 1 endpoint per port no need for addresses. */ 173 ov772x_1_1: endpoint { 174 bus-width = <8>; 175 remote-endpoint = <&ceu0_1>; 176 hsync-active = <1>; 177 vsync-active = <0>; /* Who came up with an 178 inverter here ?... */ 179 data-active = <1>; 180 pclk-sample = <1>; 181 }; 182 }; 183 }; 184 185 imx074: camera@0x1a { 186 compatible = "sony,imx074"; 187 reg = <0x1a>; 188 vddio-supply = <®ulator1>; 189 vddcore-supply = <®ulator2>; 190 191 clock-frequency = <30000000>; /* Shared clock with ov772x_1 */ 192 clocks = <&mclk 0>; 193 clock-names = "sysclk"; /* Assuming this is the 194 name in the datasheet */ 195 port { 196 imx074_1: endpoint { 197 clock-lanes = <0>; 198 data-lanes = <1 2>; 199 remote-endpoint = <&csi2_1>; 200 }; 201 }; 202 }; 203 }; 204 205 csi2: csi2@0xffc90000 { 206 compatible = "renesas,sh-mobile-csi2"; 207 reg = <0xffc90000 0x1000>; 208 interrupts = <0x17a0>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 port@1 { 213 compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */ 214 reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S, 215 PHY_M has port address 0, 216 is unused. */ 217 csi2_1: endpoint { 218 clock-lanes = <0>; 219 data-lanes = <2 1>; 220 remote-endpoint = <&imx074_1>; 221 }; 222 }; 223 port@2 { 224 reg = <2>; /* port 2: link to the CEU */ 225 226 csi2_2: endpoint { 227 remote-endpoint = <&ceu0_0>; 228 }; 229 }; 230 }; 231