xref: /linux/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx-shim.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI J721E CSI2RX Shim
8
9description: |
10  The TI J721E CSI2RX Shim is a wrapper around Cadence CSI2RX bridge that
11  enables sending captured frames to memory over PSI-L DMA. In the J721E
12  Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the
13  CSI_RX_IF section.
14
15maintainers:
16  - Jai Luthra <jai.luthra@linux.dev>
17
18properties:
19  compatible:
20    const: ti,j721e-csi2rx-shim
21
22  dmas:
23    maxItems: 1
24
25  dma-names:
26    items:
27      - const: rx0
28
29  reg:
30    maxItems: 1
31
32  power-domains:
33    maxItems: 1
34
35  ranges: true
36
37  "#address-cells": true
38
39  "#size-cells": true
40
41patternProperties:
42  "^csi-bridge@":
43    type: object
44    description: CSI2 bridge node.
45    $ref: cdns,csi2rx.yaml#
46
47required:
48  - compatible
49  - reg
50  - dmas
51  - dma-names
52  - power-domains
53  - ranges
54  - "#address-cells"
55  - "#size-cells"
56
57additionalProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/soc/ti,sci_pm_domain.h>
62
63    ti_csi2rx0: ticsi2rx@4500000 {
64        compatible = "ti,j721e-csi2rx-shim";
65        dmas = <&main_udmap 0x4940>;
66        dma-names = "rx0";
67        reg = <0x4500000 0x1000>;
68        power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
69        #address-cells = <1>;
70        #size-cells = <1>;
71        ranges;
72
73        cdns_csi2rx: csi-bridge@4504000 {
74            compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
75            reg = <0x4504000 0x1000>;
76            clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
77              <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
78            clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
79              "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
80            phys = <&dphy0>;
81            phy-names = "dphy";
82
83            ports {
84                #address-cells = <1>;
85                #size-cells = <0>;
86
87                csi2_0: port@0 {
88
89                    reg = <0>;
90
91                    csi2rx0_in_sensor: endpoint {
92                        remote-endpoint = <&csi2_cam0>;
93                        bus-type = <4>; /* CSI2 DPHY. */
94                        clock-lanes = <0>;
95                        data-lanes = <1 2>;
96                    };
97                };
98            };
99        };
100    };
101