xref: /linux/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/st,stm32-dcmipp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 DCMIPP Digital Camera Memory Interface Pixel Processor
8
9maintainers:
10  - Hugues Fruchet <hugues.fruchet@foss.st.com>
11  - Alain Volmat <alain.volmat@foss.st.com>
12
13properties:
14  compatible:
15    const: st,stm32mp13-dcmipp
16
17  reg:
18    maxItems: 1
19
20  interrupts:
21    maxItems: 1
22
23  clocks:
24    maxItems: 1
25
26  resets:
27    maxItems: 1
28
29  port:
30    $ref: /schemas/graph.yaml#/$defs/port-base
31    unevaluatedProperties: false
32    description:
33      DCMIPP supports a single port node with parallel bus.
34
35    properties:
36      endpoint:
37        $ref: video-interfaces.yaml#
38        unevaluatedProperties: false
39
40        properties:
41          bus-type:
42            enum: [5, 6]
43            default: 5
44
45          bus-width:
46            enum: [8, 10, 12, 14]
47            default: 8
48
49          pclk-sample: true
50          hsync-active: true
51          vsync-active: true
52
53        required:
54          - pclk-sample
55
56required:
57  - compatible
58  - reg
59  - interrupts
60  - clocks
61  - resets
62  - port
63
64additionalProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/interrupt-controller/arm-gic.h>
69    #include <dt-bindings/clock/stm32mp13-clks.h>
70    #include <dt-bindings/reset/stm32mp13-resets.h>
71    dcmipp@5a000000 {
72        compatible = "st,stm32mp13-dcmipp";
73        reg = <0x5a000000 0x400>;
74        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
75        resets = <&rcc DCMIPP_R>;
76        clocks = <&rcc DCMIPP_K>;
77
78        port {
79             endpoint {
80                   remote-endpoint = <&mipid02_2>;
81                   bus-width = <8>;
82                   hsync-active = <0>;
83                   vsync-active = <0>;
84                   pclk-sample = <0>;
85             };
86        };
87    };
88
89...
90