xref: /linux/Documentation/devicetree/bindings/media/rockchip-isp1.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Image Signal Processing unit v1
8
9maintainers:
10  - Helen Koike <helen.koike@collabora.com>
11
12description: |
13  Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
14  which contains image processing, scaling, and compression functions.
15
16properties:
17  compatible:
18    enum:
19      - fsl,imx8mp-isp
20      - rockchip,px30-cif-isp
21      - rockchip,rk3399-cif-isp
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    minItems: 1
28    maxItems: 3
29
30  interrupt-names:
31    items:
32      - const: isp
33      - const: mi
34      - const: mipi
35
36  clocks:
37    minItems: 3
38    items:
39      # isp0 and isp1
40      - description: ISP clock (for imx8mp, clk)
41      - description: ISP AXI clock (for imx8mp, m_hclk)
42      - description: ISP AHB clock (for imx8mp, hclk)
43      # only for isp1
44      - description: ISP Pixel clock
45
46  clock-names:
47    minItems: 3
48    items:
49      # isp0 and isp1
50      - const: isp
51      - const: aclk
52      - const: hclk
53      # only for isp1
54      - const: pclk
55
56  fsl,blk-ctrl:
57    $ref: /schemas/types.yaml#/definitions/phandle-array
58    maxItems: 1
59    description:
60      A phandle to the media block control for the ISP, followed by a cell
61      containing the index of the gasket.
62
63  iommus:
64    maxItems: 1
65
66  phys:
67    maxItems: 1
68    description: phandle for the PHY port
69
70  phy-names:
71    const: dphy
72
73  power-domains:
74    minItems: 1
75    items:
76      - description: ISP power domain
77      - description: MIPI CSI-2 power domain
78
79  power-domain-names:
80    minItems: 1
81    items:
82      - const: isp
83      - const: csi2
84
85  ports:
86    $ref: /schemas/graph.yaml#/properties/ports
87
88    properties:
89      port@0:
90        $ref: /schemas/graph.yaml#/$defs/port-base
91        unevaluatedProperties: false
92        description: connection point for sensors at MIPI-DPHY RX0
93
94        properties:
95          endpoint:
96            $ref: video-interfaces.yaml#
97            unevaluatedProperties: false
98
99            properties:
100              data-lanes:
101                minItems: 1
102                maxItems: 4
103
104      port@1:
105        $ref: /schemas/graph.yaml#/$defs/port-base
106        unevaluatedProperties: false
107        description: connection point for input on the parallel interface
108
109        properties:
110          endpoint:
111            $ref: video-interfaces.yaml#
112            unevaluatedProperties: false
113
114            properties:
115              bus-type:
116                enum: [5, 6]
117
118            required:
119              - bus-type
120
121    anyOf:
122      - required:
123          - port@0
124      - required:
125          - port@1
126
127required:
128  - compatible
129  - reg
130  - interrupts
131  - clocks
132  - clock-names
133  - power-domains
134  - ports
135
136allOf:
137  - if:
138      properties:
139        compatible:
140          contains:
141            const: rockchip,rk3399-cif-isp
142    then:
143      properties:
144        clocks:
145          minItems: 3
146          maxItems: 4
147        clock-names:
148          minItems: 3
149          maxItems: 4
150
151  - if:
152      properties:
153        compatible:
154          contains:
155            const: rockchip,px30-cif-isp
156    then:
157      required:
158        - interrupt-names
159
160  - if:
161      properties:
162        compatible:
163          contains:
164            const: fsl,imx8mp-isp
165    then:
166      properties:
167        clocks:
168          minItems: 4
169        clock-names:
170          minItems: 4
171        iommus: false
172        phys: false
173        phy-names: false
174        power-domains:
175          minItems: 2
176        power-domain-names:
177          minItems: 2
178      required:
179        - fsl,blk-ctrl
180        - power-domain-names
181    else:
182      properties:
183        fsl,blk-ctrl: false
184        power-domains:
185          maxItems: 1
186        power-domain-names: false
187      required:
188        - iommus
189        - phys
190        - phy-names
191
192additionalProperties: false
193
194examples:
195  - |
196
197    #include <dt-bindings/clock/rk3399-cru.h>
198    #include <dt-bindings/interrupt-controller/arm-gic.h>
199    #include <dt-bindings/power/rk3399-power.h>
200
201    parent0: parent {
202        #address-cells = <2>;
203        #size-cells = <2>;
204
205        isp0: isp0@ff910000 {
206            compatible = "rockchip,rk3399-cif-isp";
207            reg = <0x0 0xff910000 0x0 0x4000>;
208            interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
209            clocks = <&cru SCLK_ISP0>,
210                     <&cru ACLK_ISP0_WRAPPER>,
211                     <&cru HCLK_ISP0_WRAPPER>;
212            clock-names = "isp", "aclk", "hclk";
213            iommus = <&isp0_mmu>;
214            phys = <&dphy>;
215            phy-names = "dphy";
216            power-domains = <&power RK3399_PD_ISP0>;
217
218            ports {
219                #address-cells = <1>;
220                #size-cells = <0>;
221
222                port@0 {
223                    reg = <0>;
224                    #address-cells = <1>;
225                    #size-cells = <0>;
226
227                    mipi_in_wcam: endpoint@0 {
228                        reg = <0>;
229                        remote-endpoint = <&wcam_out>;
230                        data-lanes = <1 2>;
231                    };
232
233                    mipi_in_ucam: endpoint@1 {
234                        reg = <1>;
235                        remote-endpoint = <&ucam_out>;
236                        data-lanes = <1>;
237                    };
238                };
239            };
240        };
241
242        i2c7: i2c {
243            #address-cells = <1>;
244            #size-cells = <0>;
245
246            wcam: camera@36 {
247                compatible = "ovti,ov5695";
248                reg = <0x36>;
249                clocks = <&cru SCLK_TESTCLKOUT1>;
250
251                port {
252                    wcam_out: endpoint {
253                        remote-endpoint = <&mipi_in_wcam>;
254                        data-lanes = <1 2>;
255                    };
256                };
257            };
258
259            ucam: camera@3c {
260                compatible = "ovti,ov2685";
261                reg = <0x3c>;
262
263                clocks = <&cru SCLK_TESTCLKOUT1>;
264                clock-names = "xvclk";
265
266                avdd-supply = <&pp2800_cam>;
267                dovdd-supply = <&pp1800>;
268                dvdd-supply = <&pp1800>;
269
270                port {
271                    ucam_out: endpoint {
272                        remote-endpoint = <&mipi_in_ucam>;
273                        data-lanes = <1>;
274                    };
275                };
276            };
277        };
278    };
279
280  - |
281
282    #include <dt-bindings/interrupt-controller/arm-gic.h>
283    #include <dt-bindings/power/px30-power.h>
284
285    parent1: parent {
286        #address-cells = <2>;
287        #size-cells = <2>;
288
289        isp: isp@ff4a0000 {
290            compatible = "rockchip,px30-cif-isp";
291            reg = <0x0 0xff4a0000 0x0 0x8000>;
292            interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
293                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
294                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
295            interrupt-names = "isp", "mi", "mipi";
296            clocks = <&cru SCLK_ISP0>,
297                     <&cru ACLK_ISP0_WRAPPER>,
298                     <&cru HCLK_ISP0_WRAPPER>,
299                     <&cru PCLK_ISP1_WRAPPER>;
300            clock-names = "isp", "aclk", "hclk", "pclk";
301            iommus = <&isp_mmu>;
302            phys = <&csi_dphy>;
303            phy-names = "dphy";
304            power-domains = <&power PX30_PD_VI>;
305
306            ports {
307                #address-cells = <1>;
308                #size-cells = <0>;
309
310                port@0 {
311                    reg = <0>;
312                    #address-cells = <1>;
313                    #size-cells = <0>;
314
315                    mipi_in_ucam1: endpoint@0 {
316                        reg = <0>;
317                        remote-endpoint = <&ucam1_out>;
318                        data-lanes = <1 2>;
319                    };
320                };
321            };
322        };
323
324        i2c2: i2c {
325            #address-cells = <1>;
326            #size-cells = <0>;
327
328            ov5695: camera@36 {
329                compatible = "ovti,ov5647";
330                reg = <0x36>;
331                clocks = <&cru SCLK_CIF_OUT>;
332
333                port {
334                    ucam1_out: endpoint {
335                        remote-endpoint = <&mipi_in_ucam1>;
336                        data-lanes = <1 2>;
337                    };
338                };
339            };
340        };
341    };
342