1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/rockchip,vdec.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip Video Decoder (VDec) 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12description: |- 13 Rockchip SoCs have variants of the same stateless Video Decoder that can 14 decodes H.264, HEVC, VP9 and AV1 streams, depending on the variant. 15 16properties: 17 compatible: 18 oneOf: 19 - const: rockchip,rk3399-vdec 20 - const: rockchip,rk3576-vdec 21 - const: rockchip,rk3588-vdec 22 - items: 23 - enum: 24 - rockchip,rk3228-vdec 25 - rockchip,rk3328-vdec 26 - const: rockchip,rk3399-vdec 27 28 reg: 29 minItems: 1 30 items: 31 - description: The function configuration registers base 32 - description: The link table configuration registers base 33 - description: The cache configuration registers base 34 35 reg-names: 36 items: 37 - const: function 38 - const: link 39 - const: cache 40 41 interrupts: 42 maxItems: 1 43 44 clocks: 45 minItems: 4 46 items: 47 - description: The Video Decoder AXI interface clock 48 - description: The Video Decoder AHB interface clock 49 - description: The Video Decoded CABAC clock 50 - description: The Video Decoder core clock 51 - description: The Video decoder HEVC CABAC clock 52 53 clock-names: 54 minItems: 4 55 items: 56 - const: axi 57 - const: ahb 58 - const: cabac 59 - const: core 60 - const: hevc_cabac 61 62 assigned-clocks: true 63 64 assigned-clock-rates: true 65 66 resets: 67 items: 68 - description: The Video Decoder AXI interface reset 69 - description: The Video Decoder AHB interface reset 70 - description: The Video Decoded CABAC reset 71 - description: The Video Decoder core reset 72 - description: The Video decoder HEVC CABAC reset 73 74 reset-names: 75 items: 76 - const: axi 77 - const: ahb 78 - const: cabac 79 - const: core 80 - const: hevc_cabac 81 82 power-domains: 83 maxItems: 1 84 85 iommus: 86 maxItems: 1 87 88 sram: 89 $ref: /schemas/types.yaml#/definitions/phandle 90 description: | 91 phandle to a reserved on-chip SRAM regions. 92 Some SoCs, like rk3588 provide on-chip SRAM to store temporary 93 buffers during decoding. 94 95required: 96 - compatible 97 - reg 98 - interrupts 99 - clocks 100 - clock-names 101 - power-domains 102 103allOf: 104 - if: 105 properties: 106 compatible: 107 contains: 108 enum: 109 - rockchip,rk3576-vdec 110 - rockchip,rk3588-vdec 111 then: 112 properties: 113 reg: 114 minItems: 3 115 reg-names: 116 minItems: 3 117 clocks: 118 minItems: 5 119 clock-names: 120 minItems: 5 121 resets: 122 minItems: 5 123 reset-names: 124 minItems: 5 125 else: 126 properties: 127 reg: 128 maxItems: 1 129 reg-names: false 130 clocks: 131 maxItems: 4 132 clock-names: 133 maxItems: 4 134 resets: false 135 reset-names: false 136 sram: false 137 138additionalProperties: false 139 140examples: 141 - | 142 #include <dt-bindings/interrupt-controller/arm-gic.h> 143 #include <dt-bindings/clock/rk3399-cru.h> 144 #include <dt-bindings/power/rk3399-power.h> 145 146 vdec: video-codec@ff660000 { 147 compatible = "rockchip,rk3399-vdec"; 148 reg = <0xff660000 0x400>; 149 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 150 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 151 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 152 clock-names = "axi", "ahb", "cabac", "core"; 153 power-domains = <&power RK3399_PD_VDU>; 154 iommus = <&vdec_mmu>; 155 }; 156 157... 158