xref: /linux/Documentation/devicetree/bindings/media/renesas,vsp1.yaml (revision a6021aa24f6417416d93318bbfa022ab229c33c8) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/renesas,vsp1.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VSP Video Processing Engine
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11
12description:
13  The VSP is a video processing engine that supports up-/down-scaling, alpha
14  blending, color space conversion and various other image processing features.
15  It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - renesas,r9a07g044-vsp2 # RZ/G2L
22          - renesas,vsp1 # R-Car Gen2 and RZ/G1
23          - renesas,vsp2 # R-Car Gen3 and RZ/G2
24      - items:
25          - enum:
26              - renesas,r9a07g043u-vsp2   # RZ/G2UL
27              - renesas,r9a07g054-vsp2    # RZ/V2L
28          - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks: true
37  clock-names: true
38
39  power-domains:
40    maxItems: 1
41
42  resets:
43    maxItems: 1
44
45  renesas,fcp:
46    $ref: /schemas/types.yaml#/definitions/phandle
47    description:
48      A phandle referencing the FCP that handles memory accesses for the VSP.
49
50required:
51  - compatible
52  - reg
53  - interrupts
54  - clocks
55  - power-domains
56  - resets
57
58additionalProperties: false
59
60allOf:
61  - if:
62      properties:
63        compatible:
64          contains:
65            const: renesas,vsp1
66    then:
67      properties:
68        renesas,fcp: false
69    else:
70      required:
71        - renesas,fcp
72
73  - if:
74      properties:
75        compatible:
76          contains:
77            const: renesas,r9a07g044-vsp2
78    then:
79      properties:
80        clocks:
81          items:
82            - description: Main clock
83            - description: Register access clock
84            - description: Video clock
85        clock-names:
86          items:
87            - const: aclk
88            - const: pclk
89            - const: vclk
90      required:
91        - clock-names
92    else:
93      properties:
94        clocks:
95          maxItems: 1
96        clock-names: false
97
98examples:
99  # R8A7790 (R-Car H2) VSP1-S
100  - |
101    #include <dt-bindings/clock/renesas-cpg-mssr.h>
102    #include <dt-bindings/interrupt-controller/arm-gic.h>
103    #include <dt-bindings/power/r8a7790-sysc.h>
104
105    vsp@fe928000 {
106        compatible = "renesas,vsp1";
107        reg = <0xfe928000 0x8000>;
108        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
109        clocks = <&cpg CPG_MOD 131>;
110        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
111        resets = <&cpg 131>;
112    };
113
114  # R8A77951 (R-Car H3) VSP2-BC
115  - |
116    #include <dt-bindings/clock/renesas-cpg-mssr.h>
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    #include <dt-bindings/power/r8a7795-sysc.h>
119
120    vsp@fe920000 {
121        compatible = "renesas,vsp2";
122        reg = <0xfe920000 0x8000>;
123        interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
124        clocks = <&cpg CPG_MOD 624>;
125        power-domains = <&sysc R8A7795_PD_A3VP>;
126        resets = <&cpg 624>;
127
128        renesas,fcp = <&fcpvb1>;
129    };
130...
131