xref: /linux/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml (revision 84318277d6334c6981ab326d4acc87c6a6ddc9b8)
1*ef5a75b4SDaniel Scally# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*ef5a75b4SDaniel Scally%YAML 1.2
3*ef5a75b4SDaniel Scally---
4*ef5a75b4SDaniel Scally$id: http://devicetree.org/schemas/media/renesas,r9a09g057-ivc.yaml#
5*ef5a75b4SDaniel Scally$schema: http://devicetree.org/meta-schemas/core.yaml#
6*ef5a75b4SDaniel Scally
7*ef5a75b4SDaniel Scallytitle: Renesas RZ/V2H(P) Input Video Control Block
8*ef5a75b4SDaniel Scally
9*ef5a75b4SDaniel Scallymaintainers:
10*ef5a75b4SDaniel Scally  - Daniel Scally <dan.scally@ideasonboard.com>
11*ef5a75b4SDaniel Scally
12*ef5a75b4SDaniel Scallydescription:
13*ef5a75b4SDaniel Scally  The IVC block is a module that takes video frames from memory and feeds them
14*ef5a75b4SDaniel Scally  to the Image Signal Processor for processing.
15*ef5a75b4SDaniel Scally
16*ef5a75b4SDaniel Scallyproperties:
17*ef5a75b4SDaniel Scally  compatible:
18*ef5a75b4SDaniel Scally    const: renesas,r9a09g057-ivc # RZ/V2H(P)
19*ef5a75b4SDaniel Scally
20*ef5a75b4SDaniel Scally  reg:
21*ef5a75b4SDaniel Scally    maxItems: 1
22*ef5a75b4SDaniel Scally
23*ef5a75b4SDaniel Scally  interrupts:
24*ef5a75b4SDaniel Scally    maxItems: 1
25*ef5a75b4SDaniel Scally
26*ef5a75b4SDaniel Scally  clocks:
27*ef5a75b4SDaniel Scally    items:
28*ef5a75b4SDaniel Scally      - description: Input Video Control block register access clock
29*ef5a75b4SDaniel Scally      - description: Video input data AXI bus clock
30*ef5a75b4SDaniel Scally      - description: ISP system clock
31*ef5a75b4SDaniel Scally
32*ef5a75b4SDaniel Scally  clock-names:
33*ef5a75b4SDaniel Scally    items:
34*ef5a75b4SDaniel Scally      - const: reg
35*ef5a75b4SDaniel Scally      - const: axi
36*ef5a75b4SDaniel Scally      - const: isp
37*ef5a75b4SDaniel Scally
38*ef5a75b4SDaniel Scally  power-domains:
39*ef5a75b4SDaniel Scally    maxItems: 1
40*ef5a75b4SDaniel Scally
41*ef5a75b4SDaniel Scally  resets:
42*ef5a75b4SDaniel Scally    items:
43*ef5a75b4SDaniel Scally      - description: Input Video Control block register access reset
44*ef5a75b4SDaniel Scally      - description: Video input data AXI bus reset
45*ef5a75b4SDaniel Scally      - description: ISP core reset
46*ef5a75b4SDaniel Scally
47*ef5a75b4SDaniel Scally  reset-names:
48*ef5a75b4SDaniel Scally    items:
49*ef5a75b4SDaniel Scally      - const: reg
50*ef5a75b4SDaniel Scally      - const: axi
51*ef5a75b4SDaniel Scally      - const: isp
52*ef5a75b4SDaniel Scally
53*ef5a75b4SDaniel Scally  port:
54*ef5a75b4SDaniel Scally    $ref: /schemas/graph.yaml#/properties/port
55*ef5a75b4SDaniel Scally    description: Output parallel video bus
56*ef5a75b4SDaniel Scally
57*ef5a75b4SDaniel Scally    properties:
58*ef5a75b4SDaniel Scally      endpoint:
59*ef5a75b4SDaniel Scally        $ref: /schemas/graph.yaml#/properties/endpoint
60*ef5a75b4SDaniel Scally
61*ef5a75b4SDaniel Scallyrequired:
62*ef5a75b4SDaniel Scally  - compatible
63*ef5a75b4SDaniel Scally  - reg
64*ef5a75b4SDaniel Scally  - interrupts
65*ef5a75b4SDaniel Scally  - clocks
66*ef5a75b4SDaniel Scally  - clock-names
67*ef5a75b4SDaniel Scally  - power-domains
68*ef5a75b4SDaniel Scally  - resets
69*ef5a75b4SDaniel Scally  - reset-names
70*ef5a75b4SDaniel Scally  - port
71*ef5a75b4SDaniel Scally
72*ef5a75b4SDaniel ScallyadditionalProperties: false
73*ef5a75b4SDaniel Scally
74*ef5a75b4SDaniel Scallyexamples:
75*ef5a75b4SDaniel Scally  - |
76*ef5a75b4SDaniel Scally    #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
77*ef5a75b4SDaniel Scally    #include <dt-bindings/interrupt-controller/arm-gic.h>
78*ef5a75b4SDaniel Scally
79*ef5a75b4SDaniel Scally    isp-input@16040000 {
80*ef5a75b4SDaniel Scally      compatible = "renesas,r9a09g057-ivc";
81*ef5a75b4SDaniel Scally      reg = <0x16040000 0x230>;
82*ef5a75b4SDaniel Scally
83*ef5a75b4SDaniel Scally      clocks = <&cpg CPG_MOD 0xe3>,
84*ef5a75b4SDaniel Scally               <&cpg CPG_MOD 0xe4>,
85*ef5a75b4SDaniel Scally               <&cpg CPG_MOD 0xe5>;
86*ef5a75b4SDaniel Scally      clock-names = "reg", "axi", "isp";
87*ef5a75b4SDaniel Scally
88*ef5a75b4SDaniel Scally      power-domains = <&cpg>;
89*ef5a75b4SDaniel Scally
90*ef5a75b4SDaniel Scally      resets = <&cpg 0xd4>,
91*ef5a75b4SDaniel Scally               <&cpg 0xd1>,
92*ef5a75b4SDaniel Scally               <&cpg 0xd3>;
93*ef5a75b4SDaniel Scally      reset-names = "reg", "axi", "isp";
94*ef5a75b4SDaniel Scally
95*ef5a75b4SDaniel Scally      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
96*ef5a75b4SDaniel Scally
97*ef5a75b4SDaniel Scally      port {
98*ef5a75b4SDaniel Scally        ivc_out: endpoint {
99*ef5a75b4SDaniel Scally          remote-endpoint = <&isp_in>;
100*ef5a75b4SDaniel Scally        };
101*ef5a75b4SDaniel Scally      };
102*ef5a75b4SDaniel Scally    };
103*ef5a75b4SDaniel Scally...
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