xref: /linux/Documentation/devicetree/bindings/media/renesas,fdp1.yaml (revision f4e9654a79ca015f041cb8b3848d6557309a9ba1) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car Fine Display Processor (FDP1)
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11
12description:
13  The FDP1 is a de-interlacing module which converts interlaced video to
14  progressive video. It is capable of performing pixel format conversion
15  between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are
16  supported as an input to the module.
17
18properties:
19  compatible:
20    enum:
21      - renesas,fdp1
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  power-domains:
33    maxItems: 1
34
35  renesas,fcp:
36    $ref: /schemas/types.yaml#/definitions/phandle
37    description:
38      A phandle referencing the FCP that handles memory accesses for the FDP1.
39      Not allowed on R-Car Gen2, mandatory on R-Car Gen3.
40
41required:
42  - compatible
43  - reg
44  - interrupts
45  - clocks
46  - power-domains
47
48additionalProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/clock/renesas-cpg-mssr.h>
53    #include <dt-bindings/interrupt-controller/arm-gic.h>
54    #include <dt-bindings/power/r8a7795-sysc.h>
55
56    fdp1@fe940000 {
57        compatible = "renesas,fdp1";
58        reg = <0xfe940000 0x2400>;
59        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
60        clocks = <&cpg CPG_MOD 119>;
61        power-domains = <&sysc R8A7795_PD_A3VP>;
62        renesas,fcp = <&fcpf0>;
63    };
64...
65