xref: /linux/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml (revision 184e56e77c06a7eef68a021e9d4b11a11a8ab096) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM670 Camera Subsystem (CAMSS)
8
9maintainers:
10  - Richard Acayan <mailingradian@gmail.com>
11
12description:
13  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
14
15properties:
16  compatible:
17    const: qcom,sdm670-camss
18
19  reg:
20    maxItems: 9
21
22  reg-names:
23    items:
24      - const: csid0
25      - const: csid1
26      - const: csid2
27      - const: csiphy0
28      - const: csiphy1
29      - const: csiphy2
30      - const: vfe0
31      - const: vfe1
32      - const: vfe_lite
33
34  interrupts:
35    maxItems: 9
36
37  interrupt-names:
38    items:
39      - const: csid0
40      - const: csid1
41      - const: csid2
42      - const: csiphy0
43      - const: csiphy1
44      - const: csiphy2
45      - const: vfe0
46      - const: vfe1
47      - const: vfe_lite
48
49  clocks:
50    maxItems: 22
51
52  clock-names:
53    items:
54      - const: camnoc_axi
55      - const: cpas_ahb
56      - const: csi0
57      - const: csi1
58      - const: csi2
59      - const: csiphy0
60      - const: csiphy0_timer
61      - const: csiphy1
62      - const: csiphy1_timer
63      - const: csiphy2
64      - const: csiphy2_timer
65      - const: gcc_camera_ahb
66      - const: gcc_camera_axi
67      - const: soc_ahb
68      - const: vfe0
69      - const: vfe0_axi
70      - const: vfe0_cphy_rx
71      - const: vfe1
72      - const: vfe1_axi
73      - const: vfe1_cphy_rx
74      - const: vfe_lite
75      - const: vfe_lite_cphy_rx
76
77  iommus:
78    maxItems: 4
79
80  power-domains:
81    items:
82      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
83      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
84      - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
85
86  power-domain-names:
87    items:
88      - const: ife0
89      - const: ife1
90      - const: top
91
92  vdda-phy-supply:
93    description:
94      Phandle to a regulator supply to PHY core block.
95
96  vdda-pll-supply:
97    description:
98      Phandle to 1.8V regulator supply to PHY refclk pll block.
99
100  ports:
101    $ref: /schemas/graph.yaml#/properties/ports
102
103    description:
104      CSI input ports.
105
106    properties:
107      port@0:
108        $ref: /schemas/graph.yaml#/$defs/port-base
109        unevaluatedProperties: false
110        description:
111          Input port for receiving CSI data from CSIPHY0.
112
113        properties:
114          endpoint:
115            $ref: video-interfaces.yaml#
116            unevaluatedProperties: false
117
118            properties:
119              clock-lanes:
120                maxItems: 1
121
122              data-lanes:
123                minItems: 1
124                maxItems: 4
125
126            required:
127              - clock-lanes
128              - data-lanes
129
130      port@1:
131        $ref: /schemas/graph.yaml#/$defs/port-base
132        unevaluatedProperties: false
133        description:
134          Input port for receiving CSI data from CSIPHY1.
135
136        properties:
137          endpoint:
138            $ref: video-interfaces.yaml#
139            unevaluatedProperties: false
140
141            properties:
142              clock-lanes:
143                maxItems: 1
144
145              data-lanes:
146                minItems: 1
147                maxItems: 4
148
149            required:
150              - clock-lanes
151              - data-lanes
152
153      port@2:
154        $ref: /schemas/graph.yaml#/$defs/port-base
155        unevaluatedProperties: false
156        description:
157          Input port for receiving CSI data from CSIPHY2.
158
159        properties:
160          endpoint:
161            $ref: video-interfaces.yaml#
162            unevaluatedProperties: false
163
164            properties:
165              clock-lanes:
166                maxItems: 1
167
168              data-lanes:
169                minItems: 1
170                maxItems: 4
171
172            required:
173              - clock-lanes
174              - data-lanes
175
176required:
177  - compatible
178  - reg
179  - reg-names
180  - interrupts
181  - interrupt-names
182  - clocks
183  - clock-names
184  - iommus
185  - power-domains
186  - power-domain-names
187  - vdda-phy-supply
188  - vdda-pll-supply
189
190additionalProperties: false
191
192examples:
193  - |
194    #include <dt-bindings/clock/qcom,camcc-sdm845.h>
195    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
196    #include <dt-bindings/interrupt-controller/arm-gic.h>
197
198    soc {
199        #address-cells = <2>;
200        #size-cells = <2>;
201
202        isp@acb3000 {
203            compatible = "qcom,sdm670-camss";
204
205            reg = <0 0x0acb3000 0 0x1000>,
206                  <0 0x0acba000 0 0x1000>,
207                  <0 0x0acc8000 0 0x1000>,
208                  <0 0x0ac65000 0 0x1000>,
209                  <0 0x0ac66000 0 0x1000>,
210                  <0 0x0ac67000 0 0x1000>,
211                  <0 0x0acaf000 0 0x4000>,
212                  <0 0x0acb6000 0 0x4000>,
213                  <0 0x0acc4000 0 0x4000>;
214            reg-names = "csid0",
215                        "csid1",
216                        "csid2",
217                        "csiphy0",
218                        "csiphy1",
219                        "csiphy2",
220                        "vfe0",
221                        "vfe1",
222                        "vfe_lite";
223
224            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
225                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
226                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
227                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
228                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
229                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
230                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
231                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
232                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
233            interrupt-names = "csid0",
234                              "csid1",
235                              "csid2",
236                              "csiphy0",
237                              "csiphy1",
238                              "csiphy2",
239                              "vfe0",
240                              "vfe1",
241                              "vfe_lite";
242
243            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
244                     <&camcc CAM_CC_CPAS_AHB_CLK>,
245                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
246                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
247                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
248                     <&camcc CAM_CC_CSIPHY0_CLK>,
249                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
250                     <&camcc CAM_CC_CSIPHY1_CLK>,
251                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
252                     <&camcc CAM_CC_CSIPHY2_CLK>,
253                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
254                     <&gcc GCC_CAMERA_AHB_CLK>,
255                     <&gcc GCC_CAMERA_AXI_CLK>,
256                     <&camcc CAM_CC_SOC_AHB_CLK>,
257                     <&camcc CAM_CC_IFE_0_CLK>,
258                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
259                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
260                     <&camcc CAM_CC_IFE_1_CLK>,
261                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
262                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
263                     <&camcc CAM_CC_IFE_LITE_CLK>,
264                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
265            clock-names = "camnoc_axi",
266                          "cpas_ahb",
267                          "csi0",
268                          "csi1",
269                          "csi2",
270                          "csiphy0",
271                          "csiphy0_timer",
272                          "csiphy1",
273                          "csiphy1_timer",
274                          "csiphy2",
275                          "csiphy2_timer",
276                          "gcc_camera_ahb",
277                          "gcc_camera_axi",
278                          "soc_ahb",
279                          "vfe0",
280                          "vfe0_axi",
281                          "vfe0_cphy_rx",
282                          "vfe1",
283                          "vfe1_axi",
284                          "vfe1_cphy_rx",
285                          "vfe_lite",
286                          "vfe_lite_cphy_rx";
287
288            iommus = <&apps_smmu 0x808 0x0>,
289                     <&apps_smmu 0x810 0x8>,
290                     <&apps_smmu 0xc08 0x0>,
291                     <&apps_smmu 0xc10 0x8>;
292
293            power-domains = <&camcc IFE_0_GDSC>,
294                            <&camcc IFE_1_GDSC>,
295                            <&camcc TITAN_TOP_GDSC>;
296            power-domain-names = "ife0",
297                                 "ife1",
298                                 "top";
299
300            vdda-phy-supply = <&vreg_l1a_1p225>;
301            vdda-pll-supply = <&vreg_l8a_1p8>;
302
303            ports {
304                #address-cells = <1>;
305                #size-cells = <0>;
306
307                port@0 {
308                    reg = <0>;
309
310                    csiphy_ep0: endpoint {
311                        clock-lanes = <7>;
312                        data-lanes = <0 1 2 3>;
313                        remote-endpoint = <&front_sensor_ep>;
314                    };
315                };
316            };
317        };
318    };
319