1*23ce62d2SAndrew-CT Chen* Mediatek Video Processor Unit 2*23ce62d2SAndrew-CT Chen 3*23ce62d2SAndrew-CT ChenVideo Processor Unit is a HW video controller. It controls HW Codec including 4*23ce62d2SAndrew-CT ChenH.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). 5*23ce62d2SAndrew-CT Chen 6*23ce62d2SAndrew-CT ChenRequired properties: 7*23ce62d2SAndrew-CT Chen - compatible: "mediatek,mt8173-vpu" 8*23ce62d2SAndrew-CT Chen - reg: Must contain an entry for each entry in reg-names. 9*23ce62d2SAndrew-CT Chen - reg-names: Must include the following entries: 10*23ce62d2SAndrew-CT Chen "tcm": tcm base 11*23ce62d2SAndrew-CT Chen "cfg_reg": Main configuration registers base 12*23ce62d2SAndrew-CT Chen - interrupts: interrupt number to the cpu. 13*23ce62d2SAndrew-CT Chen - clocks : clock name from clock manager 14*23ce62d2SAndrew-CT Chen - clock-names: must be main. It is the main clock of VPU 15*23ce62d2SAndrew-CT Chen 16*23ce62d2SAndrew-CT ChenOptional properties: 17*23ce62d2SAndrew-CT Chen - memory-region: phandle to a node describing memory (see 18*23ce62d2SAndrew-CT Chen Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) 19*23ce62d2SAndrew-CT Chen to be used for VPU extended memory; if not present, VPU may be located 20*23ce62d2SAndrew-CT Chen anywhere in the memory 21*23ce62d2SAndrew-CT Chen 22*23ce62d2SAndrew-CT ChenExample: 23*23ce62d2SAndrew-CT Chen vpu: vpu@10020000 { 24*23ce62d2SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 25*23ce62d2SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 26*23ce62d2SAndrew-CT Chen <0 0x10050000 0 0x100>; 27*23ce62d2SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 28*23ce62d2SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 29*23ce62d2SAndrew-CT Chen clocks = <&topckgen TOP_SCP_SEL>; 30*23ce62d2SAndrew-CT Chen clock-names = "main"; 31*23ce62d2SAndrew-CT Chen }; 32