xref: /linux/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Decode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-dec
21      - mediatek,mt8183-vcodec-dec
22
23  reg:
24    minItems: 11
25    maxItems: 11
26
27  reg-names:
28    items:
29      - const: misc
30      - const: ld
31      - const: top
32      - const: cm
33      - const: ad
34      - const: av
35      - const: pp
36      - const: hwd
37      - const: hwq
38      - const: hwb
39      - const: hwg
40
41  interrupts:
42    maxItems: 1
43
44  clocks:
45    minItems: 1
46    maxItems: 8
47
48  clock-names:
49    minItems: 1
50    maxItems: 8
51
52  assigned-clocks: true
53
54  assigned-clock-parents: true
55
56  assigned-clock-rates: true
57
58  power-domains:
59    maxItems: 1
60
61  iommus:
62    minItems: 1
63    maxItems: 32
64    description: |
65      List of the hardware port in respective IOMMU block for current Socs.
66      Refer to bindings/iommu/mediatek,iommu.yaml.
67
68  mediatek,vpu:
69    $ref: /schemas/types.yaml#/definitions/phandle
70    description:
71      Describes point to vpu.
72
73  mediatek,scp:
74    $ref: /schemas/types.yaml#/definitions/phandle
75    description:
76      Describes point to scp.
77
78  mediatek,vdecsys:
79    $ref: /schemas/types.yaml#/definitions/phandle
80    description: Phandle to the vdecsys syscon node.
81
82required:
83  - compatible
84  - reg
85  - interrupts
86  - clocks
87  - clock-names
88  - iommus
89  - mediatek,vdecsys
90
91allOf:
92  - if:
93      properties:
94        compatible:
95          contains:
96            enum:
97              - mediatek,mt8183-vcodec-dec
98
99    then:
100      required:
101        - mediatek,scp
102
103      properties:
104        clocks:
105          minItems: 1
106          maxItems: 1
107
108        clock-names:
109          items:
110            - const: vdec
111
112  - if:
113      properties:
114        compatible:
115          contains:
116            enum:
117              - mediatek,mt8173-vcodec-dec
118
119    then:
120      required:
121        - mediatek,vpu
122
123      properties:
124        clocks:
125          minItems: 8
126          maxItems: 8
127
128        clock-names:
129          items:
130            - const: vcodecpll
131            - const: univpll_d2
132            - const: clk_cci400_sel
133            - const: vdec_sel
134            - const: vdecpll
135            - const: vencpll
136            - const: venc_lt_sel
137            - const: vdec_bus_clk_src
138
139additionalProperties: false
140
141examples:
142  - |
143    #include <dt-bindings/interrupt-controller/arm-gic.h>
144    #include <dt-bindings/clock/mt8173-clk.h>
145    #include <dt-bindings/memory/mt8173-larb-port.h>
146    #include <dt-bindings/interrupt-controller/irq.h>
147    #include <dt-bindings/power/mt8173-power.h>
148
149    vcodec_dec: vcodec@16020000 {
150      compatible = "mediatek,mt8173-vcodec-dec";
151      reg = <0x16020000 0x1000>,  /*VDEC_MISC*/
152          <0x16021000 0x800>,   /*VDEC_LD*/
153          <0x16021800 0x800>,   /*VDEC_TOP*/
154          <0x16022000 0x1000>,  /*VDEC_CM*/
155          <0x16023000 0x1000>,  /*VDEC_AD*/
156          <0x16024000 0x1000>,  /*VDEC_AV*/
157          <0x16025000 0x1000>,  /*VDEC_PP*/
158          <0x16026800 0x800>,   /*VP8_VD*/
159          <0x16027000 0x800>,   /*VP6_VD*/
160          <0x16027800 0x800>,   /*VP8_VL*/
161          <0x16028400 0x400>;   /*VP9_VD*/
162      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
163      iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
164             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
165             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
166             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
167             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
168             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
169             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
170             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
171      mediatek,vpu = <&vpu>;
172      mediatek,vdecsys = <&vdecsys>;
173      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
174      clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
175             <&topckgen CLK_TOP_UNIVPLL_D2>,
176             <&topckgen CLK_TOP_CCI400_SEL>,
177             <&topckgen CLK_TOP_VDEC_SEL>,
178             <&topckgen CLK_TOP_VCODECPLL>,
179             <&apmixedsys CLK_APMIXED_VENCPLL>,
180             <&topckgen CLK_TOP_VENC_LT_SEL>,
181             <&topckgen CLK_TOP_VCODECPLL_370P5>;
182      clock-names = "vcodecpll",
183                  "univpll_d2",
184                  "clk_cci400_sel",
185                  "vdec_sel",
186                  "vdecpll",
187                  "vencpll",
188                  "venc_lt_sel",
189                  "vdec_bus_clk_src";
190      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
191                      <&topckgen CLK_TOP_CCI400_SEL>,
192                      <&topckgen CLK_TOP_VDEC_SEL>,
193                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
194                      <&apmixedsys CLK_APMIXED_VENCPLL>;
195      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
196                             <&topckgen CLK_TOP_UNIVPLL_D2>,
197                             <&topckgen CLK_TOP_VCODECPLL>;
198      assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
199    };
200