xref: /linux/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek JPEG Encoder
8
9maintainers:
10  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
11
12description:
13  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
14
15properties:
16  compatible:
17    const: mediatek,mt8195-jpgenc
18
19  power-domains:
20    maxItems: 1
21
22  iommus:
23    maxItems: 4
24    description:
25      Points to the respective IOMMU block with master port as argument, see
26      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
27      Ports are according to the HW.
28
29  dma-ranges:
30    maxItems: 1
31    description: |
32      Describes the physical address space of IOMMU maps to memory.
33
34  "#address-cells":
35    const: 2
36
37  "#size-cells":
38    const: 2
39
40  ranges: true
41
42# Required child node:
43patternProperties:
44  "^jpgenc@[0-9a-f]+$":
45    type: object
46    description:
47      The jpeg encoder hardware device node which should be added as subnodes to
48      the main jpeg node.
49
50    properties:
51      compatible:
52        const: mediatek,mt8195-jpgenc-hw
53
54      reg:
55        maxItems: 1
56
57      iommus:
58        minItems: 1
59        maxItems: 32
60        description:
61          List of the hardware port in respective IOMMU block for current Socs.
62          Refer to bindings/iommu/mediatek,iommu.yaml.
63
64      interrupts:
65        maxItems: 1
66
67      clocks:
68        maxItems: 1
69
70      clock-names:
71        items:
72          - const: jpgenc
73
74      power-domains:
75        maxItems: 1
76
77    required:
78      - compatible
79      - reg
80      - iommus
81      - interrupts
82      - clocks
83      - clock-names
84      - power-domains
85
86    additionalProperties: false
87
88required:
89  - compatible
90  - power-domains
91  - iommus
92  - dma-ranges
93  - ranges
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/memory/mt8195-memory-port.h>
101    #include <dt-bindings/interrupt-controller/irq.h>
102    #include <dt-bindings/clock/mt8195-clk.h>
103    #include <dt-bindings/power/mt8195-power.h>
104
105    soc {
106        #address-cells = <2>;
107        #size-cells = <2>;
108
109        jpgenc-master {
110            compatible = "mediatek,mt8195-jpgenc";
111            power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
112            iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
113                     <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
114                     <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
115                     <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
116            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
117            #address-cells = <2>;
118            #size-cells = <2>;
119            ranges;
120
121            jpgenc@1a030000 {
122                compatible = "mediatek,mt8195-jpgenc-hw";
123                reg = <0 0x1a030000 0 0x10000>;
124                iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
125                         <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
126                         <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
127                         <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
128                interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
129                clocks = <&vencsys CLK_VENC_JPGENC>;
130                clock-names = "jpgenc";
131                power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
132            };
133
134            jpgenc@1b030000 {
135                compatible = "mediatek,mt8195-jpgenc-hw";
136                reg = <0 0x1b030000 0 0x10000>;
137                iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
138                         <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
139                         <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
140                         <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
141                interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
142                clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
143                clock-names = "jpgenc";
144                power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
145            };
146        };
147    };
148