xref: /linux/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek JPEG Decoder
8
9maintainers:
10  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
11
12description:
13  MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
14
15properties:
16  compatible:
17    const: mediatek,mt8195-jpgdec
18
19  power-domains:
20    maxItems: 1
21
22  iommus:
23    maxItems: 6
24    description:
25      Points to the respective IOMMU block with master port as argument, see
26      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
27      Ports are according to the HW.
28
29  dma-ranges:
30    maxItems: 1
31    description: |
32      Describes the physical address space of IOMMU maps to memory.
33
34  "#address-cells":
35    const: 2
36
37  "#size-cells":
38    const: 2
39
40  ranges: true
41
42# Required child node:
43patternProperties:
44  "^jpgdec@[0-9a-f]+$":
45    type: object
46    description:
47      The jpeg decoder hardware device node which should be added as subnodes to
48      the main jpeg node.
49
50    properties:
51      compatible:
52        const: mediatek,mt8195-jpgdec-hw
53
54      reg:
55        maxItems: 1
56
57      iommus:
58        minItems: 1
59        maxItems: 32
60        description:
61          List of the hardware port in respective IOMMU block for current Socs.
62          Refer to bindings/iommu/mediatek,iommu.yaml.
63
64      interrupts:
65        maxItems: 1
66
67      clocks:
68        maxItems: 1
69
70      clock-names:
71        items:
72          - const: jpgdec
73
74      power-domains:
75        maxItems: 1
76
77    required:
78      - compatible
79      - reg
80      - iommus
81      - interrupts
82      - clocks
83      - clock-names
84      - power-domains
85
86    additionalProperties: false
87
88required:
89  - compatible
90  - power-domains
91  - iommus
92  - dma-ranges
93  - ranges
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/memory/mt8195-memory-port.h>
101    #include <dt-bindings/interrupt-controller/irq.h>
102    #include <dt-bindings/clock/mt8195-clk.h>
103    #include <dt-bindings/power/mt8195-power.h>
104
105    soc {
106        #address-cells = <2>;
107        #size-cells = <2>;
108
109        jpgdec-master {
110            compatible = "mediatek,mt8195-jpgdec";
111            power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
112            iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
113                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
114                     <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
115                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
116                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
117                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
118            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
119            #address-cells = <2>;
120            #size-cells = <2>;
121            ranges;
122
123            jpgdec@1a040000 {
124                compatible = "mediatek,mt8195-jpgdec-hw";
125                reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
126                iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
127                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
128                         <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
129                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
130                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
131                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
132                interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
133                clocks = <&vencsys CLK_VENC_JPGDEC>;
134                clock-names = "jpgdec";
135                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
136            };
137
138            jpgdec@1a050000 {
139                compatible = "mediatek,mt8195-jpgdec-hw";
140                reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
141                iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
142                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
143                         <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
144                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
145                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
146                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
147                interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
148                clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
149                clock-names = "jpgdec";
150                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
151            };
152
153            jpgdec@1b040000 {
154                compatible = "mediatek,mt8195-jpgdec-hw";
155                reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
156                iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
157                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
158                         <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
159                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
160                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
161                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
162                interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
163                clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
164                clock-names = "jpgdec";
165                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
166            };
167        };
168    };
169