xref: /linux/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml (revision 9cdd70ceb6faf1adfad1cc7b434c19143b08226e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Encode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Encode is the video encode hardware present in Mediatek
15  SoCs which supports high resolution encoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-enc-vp8
21      - mediatek,mt8173-vcodec-enc
22      - mediatek,mt8183-vcodec-enc
23      - mediatek,mt8192-vcodec-enc
24      - mediatek,mt8195-vcodec-enc
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  clocks:
33    minItems: 1
34    maxItems: 5
35
36  clock-names:
37    minItems: 1
38    maxItems: 5
39
40  assigned-clocks: true
41
42  assigned-clock-parents: true
43
44  iommus:
45    minItems: 1
46    maxItems: 32
47    description: |
48      List of the hardware port in respective IOMMU block for current Socs.
49      Refer to bindings/iommu/mediatek,iommu.yaml.
50
51  dma-ranges:
52    maxItems: 1
53    description: |
54      Describes the physical address space of IOMMU maps to memory.
55
56  mediatek,larb:
57    $ref: /schemas/types.yaml#/definitions/phandle
58    maxItems: 1
59    description: |
60      Must contain the local arbiters in the current Socs.
61
62  mediatek,vpu:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    maxItems: 1
65    description:
66      Describes point to vpu.
67
68  mediatek,scp:
69    $ref: /schemas/types.yaml#/definitions/phandle
70    maxItems: 1
71    description:
72      Describes point to scp.
73
74required:
75  - compatible
76  - reg
77  - interrupts
78  - clocks
79  - clock-names
80  - iommus
81  - assigned-clocks
82  - assigned-clock-parents
83
84allOf:
85  - if:
86      properties:
87        compatible:
88          contains:
89            enum:
90              - mediatek,mt8183-vcodec-enc
91              - mediatek,mt8192-vcodec-enc
92
93    then:
94      required:
95        - mediatek,scp
96
97  - if:
98      properties:
99        compatible:
100          contains:
101            enum:
102              - mediatek,mt8173-vcodec-enc-vp8
103              - mediatek,mt8173-vcodec-enc
104
105    then:
106      required:
107        - mediatek,vpu
108
109  - if:
110      properties:
111        compatible:
112          enum:
113            - mediatek,mt8173-vcodec-enc
114            - mediatek,mt8192-vcodec-enc
115            - mediatek,mt8173-vcodec-enc
116
117    then:
118      properties:
119        clock:
120          items:
121            minItems: 1
122            maxItems: 1
123        clock-names:
124          items:
125            - const: venc_sel
126    else:  # for vp8 hw decoder
127      properties:
128        clock:
129          items:
130            minItems: 1
131            maxItems: 1
132        clock-names:
133          items:
134            - const: venc_lt_sel
135
136additionalProperties: false
137
138examples:
139  - |
140    #include <dt-bindings/interrupt-controller/arm-gic.h>
141    #include <dt-bindings/clock/mt8173-clk.h>
142    #include <dt-bindings/memory/mt8173-larb-port.h>
143    #include <dt-bindings/interrupt-controller/irq.h>
144
145    vcodec_enc_avc: vcodec@18002000 {
146      compatible = "mediatek,mt8173-vcodec-enc";
147      reg = <0x18002000 0x1000>;
148      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
149      iommus = <&iommu M4U_PORT_VENC_RCPU>,
150             <&iommu M4U_PORT_VENC_REC>,
151             <&iommu M4U_PORT_VENC_BSDMA>,
152             <&iommu M4U_PORT_VENC_SV_COMV>,
153             <&iommu M4U_PORT_VENC_RD_COMV>,
154             <&iommu M4U_PORT_VENC_CUR_LUMA>,
155             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
156             <&iommu M4U_PORT_VENC_REF_LUMA>,
157             <&iommu M4U_PORT_VENC_REF_CHROMA>,
158             <&iommu M4U_PORT_VENC_NBM_RDMA>,
159             <&iommu M4U_PORT_VENC_NBM_WDMA>;
160      mediatek,larb = <&larb3>;
161      mediatek,vpu = <&vpu>;
162      clocks = <&topckgen CLK_TOP_VENC_SEL>;
163      clock-names = "venc_sel";
164      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
165      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
166    };
167
168    vcodec_enc_vp8: vcodec@19002000 {
169      compatible = "mediatek,mt8173-vcodec-enc-vp8";
170      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
171      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
172      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
173             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
174             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
175             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
176             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
177             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
178             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
179             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
180             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
181      mediatek,larb = <&larb5>;
182      mediatek,vpu = <&vpu>;
183      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
184      clock-names = "venc_lt_sel";
185      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
186      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
187    };
188