xref: /linux/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml (revision 8048b8358031ae742c1c8f16f196f6d8070bb09f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Encode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Encode is the video encode hardware present in Mediatek
15  SoCs which supports high resolution encoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-enc-vp8
21      - mediatek,mt8173-vcodec-enc
22      - mediatek,mt8183-vcodec-enc
23      - mediatek,mt8188-vcodec-enc
24      - mediatek,mt8192-vcodec-enc
25      - mediatek,mt8195-vcodec-enc
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    minItems: 1
35    maxItems: 5
36
37  clock-names:
38    minItems: 1
39    maxItems: 5
40
41  assigned-clocks: true
42
43  assigned-clock-parents: true
44
45  iommus:
46    minItems: 1
47    maxItems: 32
48    description: |
49      List of the hardware port in respective IOMMU block for current Socs.
50      Refer to bindings/iommu/mediatek,iommu.yaml.
51
52  dma-ranges:
53    maxItems: 1
54    description: |
55      Describes the physical address space of IOMMU maps to memory.
56
57  mediatek,vpu:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      Describes point to vpu.
61
62  mediatek,scp:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    description:
65      Describes point to scp.
66
67  power-domains:
68    maxItems: 1
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - clocks
75  - clock-names
76  - iommus
77  - assigned-clocks
78  - assigned-clock-parents
79
80allOf:
81  - if:
82      properties:
83        compatible:
84          contains:
85            enum:
86              - mediatek,mt8183-vcodec-enc
87              - mediatek,mt8192-vcodec-enc
88
89    then:
90      required:
91        - mediatek,scp
92
93  - if:
94      properties:
95        compatible:
96          contains:
97            enum:
98              - mediatek,mt8173-vcodec-enc-vp8
99              - mediatek,mt8173-vcodec-enc
100
101    then:
102      required:
103        - mediatek,vpu
104
105  - if:
106      properties:
107        compatible:
108          enum:
109            - mediatek,mt8173-vcodec-enc
110            - mediatek,mt8192-vcodec-enc
111
112    then:
113      properties:
114        clock:
115          items:
116            minItems: 1
117            maxItems: 1
118        clock-names:
119          items:
120            - const: venc_sel
121    else:  # for vp8 hw decoder
122      properties:
123        clock:
124          items:
125            minItems: 1
126            maxItems: 1
127        clock-names:
128          items:
129            - const: venc_lt_sel
130
131additionalProperties: false
132
133examples:
134  - |
135    #include <dt-bindings/interrupt-controller/arm-gic.h>
136    #include <dt-bindings/clock/mt8173-clk.h>
137    #include <dt-bindings/memory/mt8173-larb-port.h>
138    #include <dt-bindings/interrupt-controller/irq.h>
139
140    vcodec_enc_avc: vcodec@18002000 {
141      compatible = "mediatek,mt8173-vcodec-enc";
142      reg = <0x18002000 0x1000>;
143      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
144      iommus = <&iommu M4U_PORT_VENC_RCPU>,
145             <&iommu M4U_PORT_VENC_REC>,
146             <&iommu M4U_PORT_VENC_BSDMA>,
147             <&iommu M4U_PORT_VENC_SV_COMV>,
148             <&iommu M4U_PORT_VENC_RD_COMV>,
149             <&iommu M4U_PORT_VENC_CUR_LUMA>,
150             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
151             <&iommu M4U_PORT_VENC_REF_LUMA>,
152             <&iommu M4U_PORT_VENC_REF_CHROMA>,
153             <&iommu M4U_PORT_VENC_NBM_RDMA>,
154             <&iommu M4U_PORT_VENC_NBM_WDMA>;
155      mediatek,vpu = <&vpu>;
156      clocks = <&topckgen CLK_TOP_VENC_SEL>;
157      clock-names = "venc_sel";
158      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
159      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
160    };
161
162    vcodec_enc_vp8: vcodec@19002000 {
163      compatible = "mediatek,mt8173-vcodec-enc-vp8";
164      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
165      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
166      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
167             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
168             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
169             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
170             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
171             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
172             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
173             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
174             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
175      mediatek,vpu = <&vpu>;
176      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
177      clock-names = "venc_lt_sel";
178      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
179      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
180    };
181