xref: /linux/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml (revision 1ac731c529cd4d6adbce134754b51ff7d822b145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Encode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Encode is the video encode hardware present in Mediatek
15  SoCs which supports high resolution encoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-enc-vp8
21      - mediatek,mt8173-vcodec-enc
22      - mediatek,mt8183-vcodec-enc
23      - mediatek,mt8188-vcodec-enc
24      - mediatek,mt8192-vcodec-enc
25      - mediatek,mt8195-vcodec-enc
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    minItems: 1
35    maxItems: 5
36
37  clock-names:
38    minItems: 1
39    maxItems: 5
40
41  assigned-clocks: true
42
43  assigned-clock-parents: true
44
45  iommus:
46    minItems: 1
47    maxItems: 32
48    description: |
49      List of the hardware port in respective IOMMU block for current Socs.
50      Refer to bindings/iommu/mediatek,iommu.yaml.
51
52  mediatek,vpu:
53    $ref: /schemas/types.yaml#/definitions/phandle
54    description:
55      Describes point to vpu.
56
57  mediatek,scp:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      Describes point to scp.
61
62  power-domains:
63    maxItems: 1
64
65  "#address-cells":
66    const: 2
67
68  "#size-cells":
69    const: 2
70
71required:
72  - compatible
73  - reg
74  - interrupts
75  - clocks
76  - clock-names
77  - iommus
78  - assigned-clocks
79  - assigned-clock-parents
80
81allOf:
82  - if:
83      properties:
84        compatible:
85          contains:
86            enum:
87              - mediatek,mt8183-vcodec-enc
88              - mediatek,mt8188-vcodec-enc
89              - mediatek,mt8192-vcodec-enc
90              - mediatek,mt8195-vcodec-enc
91
92    then:
93      required:
94        - mediatek,scp
95
96  - if:
97      properties:
98        compatible:
99          contains:
100            enum:
101              - mediatek,mt8173-vcodec-enc-vp8
102              - mediatek,mt8173-vcodec-enc
103
104    then:
105      required:
106        - mediatek,vpu
107
108  - if:
109      properties:
110        compatible:
111          enum:
112            - mediatek,mt8173-vcodec-enc
113            - mediatek,mt8188-vcodec-enc
114            - mediatek,mt8192-vcodec-enc
115            - mediatek,mt8195-vcodec-enc
116
117    then:
118      properties:
119        clock:
120          items:
121            minItems: 1
122            maxItems: 1
123        clock-names:
124          items:
125            - const: venc_sel
126    else:  # for vp8 hw encoder
127      properties:
128        clock:
129          items:
130            minItems: 1
131            maxItems: 1
132        clock-names:
133          items:
134            - const: venc_lt_sel
135
136additionalProperties: false
137
138examples:
139  - |
140    #include <dt-bindings/interrupt-controller/arm-gic.h>
141    #include <dt-bindings/clock/mt8173-clk.h>
142    #include <dt-bindings/memory/mt8173-larb-port.h>
143    #include <dt-bindings/interrupt-controller/irq.h>
144
145    vcodec_enc_avc: vcodec@18002000 {
146      compatible = "mediatek,mt8173-vcodec-enc";
147      reg = <0x18002000 0x1000>;
148      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
149      iommus = <&iommu M4U_PORT_VENC_RCPU>,
150             <&iommu M4U_PORT_VENC_REC>,
151             <&iommu M4U_PORT_VENC_BSDMA>,
152             <&iommu M4U_PORT_VENC_SV_COMV>,
153             <&iommu M4U_PORT_VENC_RD_COMV>,
154             <&iommu M4U_PORT_VENC_CUR_LUMA>,
155             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
156             <&iommu M4U_PORT_VENC_REF_LUMA>,
157             <&iommu M4U_PORT_VENC_REF_CHROMA>,
158             <&iommu M4U_PORT_VENC_NBM_RDMA>,
159             <&iommu M4U_PORT_VENC_NBM_WDMA>;
160      mediatek,vpu = <&vpu>;
161      clocks = <&topckgen CLK_TOP_VENC_SEL>;
162      clock-names = "venc_sel";
163      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
164      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
165    };
166
167    vcodec_enc_vp8: vcodec@19002000 {
168      compatible = "mediatek,mt8173-vcodec-enc-vp8";
169      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
170      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
171      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
172             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
173             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
174             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
175             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
176             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
177             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
178             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
179             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
180      mediatek,vpu = <&vpu>;
181      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
182      clock-names = "venc_lt_sel";
183      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
184      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
185    };
186