xref: /linux/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml (revision 4f2c0a4acffbec01079c28f839422e64ddeff004) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Write DMA with Rotation
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - mediatek,mt8183-mdp3-wrot
21
22  reg:
23    maxItems: 1
24
25  mediatek,gce-client-reg:
26    $ref: /schemas/types.yaml#/definitions/phandle-array
27    items:
28      items:
29        - description: phandle of GCE
30        - description: GCE subsys id
31        - description: register offset
32        - description: register size
33    description: The register of client driver can be configured by gce with
34      4 arguments defined in this property. Each GCE subsys id is mapping to
35      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
36
37  mediatek,gce-events:
38    description:
39      The event id which is mapping to the specific hardware event signal
40      to gce. The event id is defined in the gce header
41      include/dt-bindings/gce/<chip>-gce.h of each chips.
42    $ref: /schemas/types.yaml#/definitions/uint32-array
43
44  power-domains:
45    maxItems: 1
46
47  clocks:
48    minItems: 1
49
50  iommus:
51    maxItems: 1
52
53required:
54  - compatible
55  - reg
56  - mediatek,gce-client-reg
57  - mediatek,gce-events
58  - power-domains
59  - clocks
60  - iommus
61
62additionalProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/mt8183-clk.h>
67    #include <dt-bindings/gce/mt8183-gce.h>
68    #include <dt-bindings/power/mt8183-power.h>
69    #include <dt-bindings/memory/mt8183-larb-port.h>
70
71    mdp3_wrot0: mdp3-wrot0@14005000 {
72      compatible = "mediatek,mt8183-mdp3-wrot";
73      reg = <0x14005000 0x1000>;
74      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
75      mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
76                            <CMDQ_EVENT_MDP_WROT0_EOF>;
77      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
78      clocks = <&mmsys CLK_MM_MDP_WROT0>;
79      iommus = <&iommu>;
80    };
81