xref: /linux/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml (revision 4f2c0a4acffbec01079c28f839422e64ddeff004) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Resizer
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  One of Media Data Path 3 (MDP3) components used to do frame resizing.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - mediatek,mt8183-mdp3-rsz
21
22  reg:
23    maxItems: 1
24
25  mediatek,gce-client-reg:
26    $ref: /schemas/types.yaml#/definitions/phandle-array
27    items:
28      items:
29        - description: phandle of GCE
30        - description: GCE subsys id
31        - description: register offset
32        - description: register size
33    description: The register of client driver can be configured by gce with
34      4 arguments defined in this property. Each GCE subsys id is mapping to
35      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
36
37  mediatek,gce-events:
38    description:
39      The event id which is mapping to the specific hardware event signal
40      to gce. The event id is defined in the gce header
41      include/dt-bindings/gce/<chip>-gce.h of each chips.
42    $ref: /schemas/types.yaml#/definitions/uint32-array
43
44  clocks:
45    minItems: 1
46
47required:
48  - compatible
49  - reg
50  - mediatek,gce-client-reg
51  - mediatek,gce-events
52  - clocks
53
54additionalProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/clock/mt8183-clk.h>
59    #include <dt-bindings/gce/mt8183-gce.h>
60
61    mdp3_rsz0: mdp3-rsz0@14003000 {
62      compatible = "mediatek,mt8183-mdp3-rsz";
63      reg = <0x14003000 0x1000>;
64      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
65      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
66                            <CMDQ_EVENT_MDP_RSZ0_EOF>;
67      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
68    };
69
70    mdp3_rsz1: mdp3-rsz1@14004000 {
71      compatible = "mediatek,mt8183-mdp3-rsz";
72      reg = <0x14004000 0x1000>;
73      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
74      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
75                            <CMDQ_EVENT_MDP_RSZ1_EOF>;
76      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
77    };
78