xref: /linux/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml (revision be3382ecdf317f005e7d47356d0a9256cc36dd88) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Read Direct Memory Access
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
15  It contains one line buffer to store the sufficient pixel data, and
16  must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8183-mdp3-rdma
26          - mediatek,mt8195-mdp3-rdma
27          - mediatek,mt8195-vdo1-rdma
28      - items:
29          - const: mediatek,mt8188-vdo1-rdma
30          - const: mediatek,mt8195-vdo1-rdma
31
32  reg:
33    maxItems: 1
34
35  mediatek,gce-client-reg:
36    $ref: /schemas/types.yaml#/definitions/phandle-array
37    items:
38      items:
39        - description: phandle of GCE
40        - description: GCE subsys id
41        - description: register offset
42        - description: register size
43    description: The register of client driver can be configured by gce with
44      4 arguments defined in this property. Each GCE subsys id is mapping to
45      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
46
47  mediatek,gce-events:
48    description:
49      The event id which is mapping to the specific hardware event signal
50      to gce. The event id is defined in the gce header
51      include/dt-bindings/gce/<chip>-gce.h of each chips.
52    $ref: /schemas/types.yaml#/definitions/uint32-array
53
54  mediatek,scp:
55    $ref: /schemas/types.yaml#/definitions/phandle
56    description:
57      Phandle to the System Control Processor (SCP) used for initializing
58      and stopping the MDP3, for sending frame data locations to the MDP3's
59      VPU and to install Inter-Processor Interrupt handlers to control
60      processing states.
61
62  power-domains:
63    maxItems: 1
64
65  clocks:
66    items:
67      - description: RDMA clock
68      - description: RSZ clock
69    minItems: 1
70
71  iommus:
72    maxItems: 1
73
74  mboxes:
75    items:
76      - description: used for 1st data pipe from RDMA
77      - description: used for 2nd data pipe from RDMA
78      - description: used for 3rd data pipe from RDMA
79      - description: used for 4th data pipe from RDMA
80      - description: used for the data pipe from SPLIT
81    minItems: 1
82
83  interrupts:
84    maxItems: 1
85
86  '#dma-cells':
87    const: 1
88
89required:
90  - compatible
91  - reg
92  - mediatek,gce-client-reg
93  - power-domains
94  - clocks
95  - iommus
96  - '#dma-cells'
97
98allOf:
99  - if:
100      properties:
101        compatible:
102          contains:
103            const: mediatek,mt8183-mdp3-rdma
104
105    then:
106      properties:
107        clocks:
108          minItems: 2
109
110        mboxes:
111          minItems: 2
112
113      required:
114        - mboxes
115        - mediatek,gce-events
116
117  - if:
118      properties:
119        compatible:
120          contains:
121            const: mediatek,mt8195-mdp3-rdma
122
123    then:
124      properties:
125        clocks:
126          maxItems: 1
127
128        mboxes:
129          minItems: 5
130
131      required:
132        - mediatek,gce-events
133
134  - if:
135      properties:
136        compatible:
137          contains:
138            const: mediatek,mt8195-vdo1-rdma
139
140    then:
141      properties:
142        clocks:
143          maxItems: 1
144
145additionalProperties: false
146
147examples:
148  - |
149    #include <dt-bindings/clock/mt8183-clk.h>
150    #include <dt-bindings/gce/mt8183-gce.h>
151    #include <dt-bindings/power/mt8183-power.h>
152    #include <dt-bindings/memory/mt8183-larb-port.h>
153
154    dma-controller@14001000 {
155        compatible = "mediatek,mt8183-mdp3-rdma";
156        reg = <0x14001000 0x1000>;
157        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
158        mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
159                              <CMDQ_EVENT_MDP_RDMA0_EOF>;
160        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
161        clocks = <&mmsys CLK_MM_MDP_RDMA0>,
162                 <&mmsys CLK_MM_MDP_RSZ1>;
163        iommus = <&iommu>;
164        mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
165                 <&gce 21 CMDQ_THR_PRIO_LOWEST>;
166        #dma-cells = <1>;
167    };
168