xref: /linux/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml (revision a60577cef7de982166baa132a8423f413b617b63) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Read Direct Memory Access
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
15  It contains one line buffer to store the sufficient pixel data, and
16  must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    items:
24      - const: mediatek,mt8183-mdp3-rdma
25
26  reg:
27    maxItems: 1
28
29  mediatek,gce-client-reg:
30    $ref: /schemas/types.yaml#/definitions/phandle-array
31    items:
32      items:
33        - description: phandle of GCE
34        - description: GCE subsys id
35        - description: register offset
36        - description: register size
37    description: The register of client driver can be configured by gce with
38      4 arguments defined in this property. Each GCE subsys id is mapping to
39      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
40
41  mediatek,gce-events:
42    description:
43      The event id which is mapping to the specific hardware event signal
44      to gce. The event id is defined in the gce header
45      include/dt-bindings/gce/<chip>-gce.h of each chips.
46    $ref: /schemas/types.yaml#/definitions/uint32-array
47
48  mediatek,scp:
49    $ref: /schemas/types.yaml#/definitions/phandle
50    description:
51      Phandle to the System Control Processor (SCP) used for initializing
52      and stopping the MDP3, for sending frame data locations to the MDP3's
53      VPU and to install Inter-Processor Interrupt handlers to control
54      processing states.
55
56  power-domains:
57    maxItems: 1
58
59  clocks:
60    items:
61      - description: RDMA clock
62      - description: RSZ clock
63
64  iommus:
65    maxItems: 1
66
67  mboxes:
68    items:
69      - description: used for 1st data pipe from RDMA
70      - description: used for 2nd data pipe from RDMA
71
72required:
73  - compatible
74  - reg
75  - mediatek,gce-client-reg
76  - mediatek,gce-events
77  - power-domains
78  - clocks
79  - iommus
80  - mboxes
81
82additionalProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/mt8183-clk.h>
87    #include <dt-bindings/gce/mt8183-gce.h>
88    #include <dt-bindings/power/mt8183-power.h>
89    #include <dt-bindings/memory/mt8183-larb-port.h>
90
91    mdp3_rdma0: mdp3-rdma0@14001000 {
92      compatible = "mediatek,mt8183-mdp3-rdma";
93      reg = <0x14001000 0x1000>;
94      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
95      mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
96                            <CMDQ_EVENT_MDP_RDMA0_EOF>;
97      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
98      clocks = <&mmsys CLK_MM_MDP_RDMA0>,
99               <&mmsys CLK_MM_MDP_RSZ1>;
100      iommus = <&iommu>;
101      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
102               <&gce 21 CMDQ_THR_PRIO_LOWEST>;
103    };
104