14ad7b396SMoudy Ho# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24ad7b396SMoudy Ho%YAML 1.2 34ad7b396SMoudy Ho--- 44ad7b396SMoudy Ho$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# 54ad7b396SMoudy Ho$schema: http://devicetree.org/meta-schemas/core.yaml# 64ad7b396SMoudy Ho 74ad7b396SMoudy Hotitle: MediaTek Read Direct Memory Access 84ad7b396SMoudy Ho 94ad7b396SMoudy Homaintainers: 104ad7b396SMoudy Ho - Matthias Brugger <matthias.bgg@gmail.com> 114ad7b396SMoudy Ho - Moudy Ho <moudy.ho@mediatek.com> 124ad7b396SMoudy Ho 134ad7b396SMoudy Hodescription: | 144ad7b396SMoudy Ho MediaTek Read Direct Memory Access(RDMA) component used to do read DMA. 154ad7b396SMoudy Ho It contains one line buffer to store the sufficient pixel data, and 164ad7b396SMoudy Ho must be siblings to the central MMSYS_CONFIG node. 174ad7b396SMoudy Ho For a description of the MMSYS_CONFIG binding, see 184ad7b396SMoudy Ho Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 194ad7b396SMoudy Ho for details. 204ad7b396SMoudy Ho 214ad7b396SMoudy Hoproperties: 224ad7b396SMoudy Ho compatible: 233bae0d63SMoudy Ho oneOf: 243bae0d63SMoudy Ho - enum: 253bae0d63SMoudy Ho - mediatek,mt8183-mdp3-rdma 26*f0c9cafdSMoudy Ho - mediatek,mt8195-mdp3-rdma 273bae0d63SMoudy Ho - mediatek,mt8195-vdo1-rdma 283bae0d63SMoudy Ho - items: 293bae0d63SMoudy Ho - const: mediatek,mt8188-vdo1-rdma 303bae0d63SMoudy Ho - const: mediatek,mt8195-vdo1-rdma 314ad7b396SMoudy Ho 324ad7b396SMoudy Ho reg: 334ad7b396SMoudy Ho maxItems: 1 344ad7b396SMoudy Ho 354ad7b396SMoudy Ho mediatek,gce-client-reg: 36ab190665SRob Herring $ref: /schemas/types.yaml#/definitions/phandle-array 374ad7b396SMoudy Ho items: 384ad7b396SMoudy Ho items: 394ad7b396SMoudy Ho - description: phandle of GCE 404ad7b396SMoudy Ho - description: GCE subsys id 414ad7b396SMoudy Ho - description: register offset 424ad7b396SMoudy Ho - description: register size 434ad7b396SMoudy Ho description: The register of client driver can be configured by gce with 444ad7b396SMoudy Ho 4 arguments defined in this property. Each GCE subsys id is mapping to 454ad7b396SMoudy Ho a client defined in the header include/dt-bindings/gce/<chip>-gce.h. 464ad7b396SMoudy Ho 474ad7b396SMoudy Ho mediatek,gce-events: 484ad7b396SMoudy Ho description: 494ad7b396SMoudy Ho The event id which is mapping to the specific hardware event signal 504ad7b396SMoudy Ho to gce. The event id is defined in the gce header 514ad7b396SMoudy Ho include/dt-bindings/gce/<chip>-gce.h of each chips. 524ad7b396SMoudy Ho $ref: /schemas/types.yaml#/definitions/uint32-array 534ad7b396SMoudy Ho 54a17cf4c6SAngeloGioacchino Del Regno mediatek,scp: 55a17cf4c6SAngeloGioacchino Del Regno $ref: /schemas/types.yaml#/definitions/phandle 56a17cf4c6SAngeloGioacchino Del Regno description: 57a17cf4c6SAngeloGioacchino Del Regno Phandle to the System Control Processor (SCP) used for initializing 58a17cf4c6SAngeloGioacchino Del Regno and stopping the MDP3, for sending frame data locations to the MDP3's 59a17cf4c6SAngeloGioacchino Del Regno VPU and to install Inter-Processor Interrupt handlers to control 60a17cf4c6SAngeloGioacchino Del Regno processing states. 61a17cf4c6SAngeloGioacchino Del Regno 624ad7b396SMoudy Ho power-domains: 634ad7b396SMoudy Ho maxItems: 1 644ad7b396SMoudy Ho 654ad7b396SMoudy Ho clocks: 664ad7b396SMoudy Ho items: 674ad7b396SMoudy Ho - description: RDMA clock 684ad7b396SMoudy Ho - description: RSZ clock 693bae0d63SMoudy Ho minItems: 1 704ad7b396SMoudy Ho 714ad7b396SMoudy Ho iommus: 724ad7b396SMoudy Ho maxItems: 1 734ad7b396SMoudy Ho 744ad7b396SMoudy Ho mboxes: 754ad7b396SMoudy Ho items: 764ad7b396SMoudy Ho - description: used for 1st data pipe from RDMA 774ad7b396SMoudy Ho - description: used for 2nd data pipe from RDMA 78*f0c9cafdSMoudy Ho - description: used for 3rd data pipe from RDMA 79*f0c9cafdSMoudy Ho - description: used for 4th data pipe from RDMA 80*f0c9cafdSMoudy Ho - description: used for the data pipe from SPLIT 813bae0d63SMoudy Ho minItems: 1 823bae0d63SMoudy Ho 833bae0d63SMoudy Ho interrupts: 843bae0d63SMoudy Ho maxItems: 1 854ad7b396SMoudy Ho 86f5f185bfSMoudy Ho '#dma-cells': 87f5f185bfSMoudy Ho const: 1 88f5f185bfSMoudy Ho 894ad7b396SMoudy Horequired: 904ad7b396SMoudy Ho - compatible 914ad7b396SMoudy Ho - reg 924ad7b396SMoudy Ho - mediatek,gce-client-reg 934ad7b396SMoudy Ho - power-domains 944ad7b396SMoudy Ho - clocks 954ad7b396SMoudy Ho - iommus 96f5f185bfSMoudy Ho - '#dma-cells' 974ad7b396SMoudy Ho 983bae0d63SMoudy HoallOf: 993bae0d63SMoudy Ho - if: 1003bae0d63SMoudy Ho properties: 1013bae0d63SMoudy Ho compatible: 1023bae0d63SMoudy Ho contains: 1033bae0d63SMoudy Ho const: mediatek,mt8183-mdp3-rdma 1043bae0d63SMoudy Ho 1053bae0d63SMoudy Ho then: 1063bae0d63SMoudy Ho properties: 1073bae0d63SMoudy Ho clocks: 1083bae0d63SMoudy Ho minItems: 2 1093bae0d63SMoudy Ho 1103bae0d63SMoudy Ho mboxes: 1113bae0d63SMoudy Ho minItems: 2 1123bae0d63SMoudy Ho 1133bae0d63SMoudy Ho required: 1143bae0d63SMoudy Ho - mboxes 1153bae0d63SMoudy Ho - mediatek,gce-events 1163bae0d63SMoudy Ho 1173bae0d63SMoudy Ho - if: 1183bae0d63SMoudy Ho properties: 1193bae0d63SMoudy Ho compatible: 1203bae0d63SMoudy Ho contains: 121*f0c9cafdSMoudy Ho const: mediatek,mt8195-mdp3-rdma 122*f0c9cafdSMoudy Ho 123*f0c9cafdSMoudy Ho then: 124*f0c9cafdSMoudy Ho properties: 125*f0c9cafdSMoudy Ho clocks: 126*f0c9cafdSMoudy Ho maxItems: 1 127*f0c9cafdSMoudy Ho 128*f0c9cafdSMoudy Ho mboxes: 129*f0c9cafdSMoudy Ho minItems: 5 130*f0c9cafdSMoudy Ho 131*f0c9cafdSMoudy Ho required: 132*f0c9cafdSMoudy Ho - mediatek,gce-events 133*f0c9cafdSMoudy Ho 134*f0c9cafdSMoudy Ho - if: 135*f0c9cafdSMoudy Ho properties: 136*f0c9cafdSMoudy Ho compatible: 137*f0c9cafdSMoudy Ho contains: 1383bae0d63SMoudy Ho const: mediatek,mt8195-vdo1-rdma 1393bae0d63SMoudy Ho 1403bae0d63SMoudy Ho then: 1413bae0d63SMoudy Ho properties: 1423bae0d63SMoudy Ho clocks: 1433bae0d63SMoudy Ho maxItems: 1 1443bae0d63SMoudy Ho 1454ad7b396SMoudy HoadditionalProperties: false 1464ad7b396SMoudy Ho 1474ad7b396SMoudy Hoexamples: 1484ad7b396SMoudy Ho - | 1494ad7b396SMoudy Ho #include <dt-bindings/clock/mt8183-clk.h> 1504ad7b396SMoudy Ho #include <dt-bindings/gce/mt8183-gce.h> 1514ad7b396SMoudy Ho #include <dt-bindings/power/mt8183-power.h> 1524ad7b396SMoudy Ho #include <dt-bindings/memory/mt8183-larb-port.h> 1534ad7b396SMoudy Ho 154f5f185bfSMoudy Ho dma-controller@14001000 { 1554ad7b396SMoudy Ho compatible = "mediatek,mt8183-mdp3-rdma"; 1564ad7b396SMoudy Ho reg = <0x14001000 0x1000>; 1574ad7b396SMoudy Ho mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1584ad7b396SMoudy Ho mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1594ad7b396SMoudy Ho <CMDQ_EVENT_MDP_RDMA0_EOF>; 1604ad7b396SMoudy Ho power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1614ad7b396SMoudy Ho clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1624ad7b396SMoudy Ho <&mmsys CLK_MM_MDP_RSZ1>; 1634ad7b396SMoudy Ho iommus = <&iommu>; 1644ad7b396SMoudy Ho mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, 1654ad7b396SMoudy Ho <&gce 21 CMDQ_THR_PRIO_LOWEST>; 166f5f185bfSMoudy Ho #dma-cells = <1>; 1674ad7b396SMoudy Ho }; 168