14ad7b396SMoudy Ho# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24ad7b396SMoudy Ho%YAML 1.2 34ad7b396SMoudy Ho--- 44ad7b396SMoudy Ho$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# 54ad7b396SMoudy Ho$schema: http://devicetree.org/meta-schemas/core.yaml# 64ad7b396SMoudy Ho 74ad7b396SMoudy Hotitle: MediaTek Read Direct Memory Access 84ad7b396SMoudy Ho 94ad7b396SMoudy Homaintainers: 104ad7b396SMoudy Ho - Matthias Brugger <matthias.bgg@gmail.com> 114ad7b396SMoudy Ho - Moudy Ho <moudy.ho@mediatek.com> 124ad7b396SMoudy Ho 134ad7b396SMoudy Hodescription: | 144ad7b396SMoudy Ho MediaTek Read Direct Memory Access(RDMA) component used to do read DMA. 154ad7b396SMoudy Ho It contains one line buffer to store the sufficient pixel data, and 164ad7b396SMoudy Ho must be siblings to the central MMSYS_CONFIG node. 174ad7b396SMoudy Ho For a description of the MMSYS_CONFIG binding, see 184ad7b396SMoudy Ho Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 194ad7b396SMoudy Ho for details. 204ad7b396SMoudy Ho 214ad7b396SMoudy Hoproperties: 224ad7b396SMoudy Ho compatible: 234ad7b396SMoudy Ho items: 244ad7b396SMoudy Ho - const: mediatek,mt8183-mdp3-rdma 254ad7b396SMoudy Ho 264ad7b396SMoudy Ho reg: 274ad7b396SMoudy Ho maxItems: 1 284ad7b396SMoudy Ho 294ad7b396SMoudy Ho mediatek,gce-client-reg: 30ab190665SRob Herring $ref: /schemas/types.yaml#/definitions/phandle-array 314ad7b396SMoudy Ho items: 324ad7b396SMoudy Ho items: 334ad7b396SMoudy Ho - description: phandle of GCE 344ad7b396SMoudy Ho - description: GCE subsys id 354ad7b396SMoudy Ho - description: register offset 364ad7b396SMoudy Ho - description: register size 374ad7b396SMoudy Ho description: The register of client driver can be configured by gce with 384ad7b396SMoudy Ho 4 arguments defined in this property. Each GCE subsys id is mapping to 394ad7b396SMoudy Ho a client defined in the header include/dt-bindings/gce/<chip>-gce.h. 404ad7b396SMoudy Ho 414ad7b396SMoudy Ho mediatek,gce-events: 424ad7b396SMoudy Ho description: 434ad7b396SMoudy Ho The event id which is mapping to the specific hardware event signal 444ad7b396SMoudy Ho to gce. The event id is defined in the gce header 454ad7b396SMoudy Ho include/dt-bindings/gce/<chip>-gce.h of each chips. 464ad7b396SMoudy Ho $ref: /schemas/types.yaml#/definitions/uint32-array 474ad7b396SMoudy Ho 48*a17cf4c6SAngeloGioacchino Del Regno mediatek,scp: 49*a17cf4c6SAngeloGioacchino Del Regno $ref: /schemas/types.yaml#/definitions/phandle 50*a17cf4c6SAngeloGioacchino Del Regno description: 51*a17cf4c6SAngeloGioacchino Del Regno Phandle to the System Control Processor (SCP) used for initializing 52*a17cf4c6SAngeloGioacchino Del Regno and stopping the MDP3, for sending frame data locations to the MDP3's 53*a17cf4c6SAngeloGioacchino Del Regno VPU and to install Inter-Processor Interrupt handlers to control 54*a17cf4c6SAngeloGioacchino Del Regno processing states. 55*a17cf4c6SAngeloGioacchino Del Regno 564ad7b396SMoudy Ho power-domains: 574ad7b396SMoudy Ho maxItems: 1 584ad7b396SMoudy Ho 594ad7b396SMoudy Ho clocks: 604ad7b396SMoudy Ho items: 614ad7b396SMoudy Ho - description: RDMA clock 624ad7b396SMoudy Ho - description: RSZ clock 634ad7b396SMoudy Ho 644ad7b396SMoudy Ho iommus: 654ad7b396SMoudy Ho maxItems: 1 664ad7b396SMoudy Ho 674ad7b396SMoudy Ho mboxes: 684ad7b396SMoudy Ho items: 694ad7b396SMoudy Ho - description: used for 1st data pipe from RDMA 704ad7b396SMoudy Ho - description: used for 2nd data pipe from RDMA 714ad7b396SMoudy Ho 724ad7b396SMoudy Horequired: 734ad7b396SMoudy Ho - compatible 744ad7b396SMoudy Ho - reg 754ad7b396SMoudy Ho - mediatek,gce-client-reg 764ad7b396SMoudy Ho - mediatek,gce-events 774ad7b396SMoudy Ho - power-domains 784ad7b396SMoudy Ho - clocks 794ad7b396SMoudy Ho - iommus 804ad7b396SMoudy Ho - mboxes 814ad7b396SMoudy Ho 824ad7b396SMoudy HoadditionalProperties: false 834ad7b396SMoudy Ho 844ad7b396SMoudy Hoexamples: 854ad7b396SMoudy Ho - | 864ad7b396SMoudy Ho #include <dt-bindings/clock/mt8183-clk.h> 874ad7b396SMoudy Ho #include <dt-bindings/gce/mt8183-gce.h> 884ad7b396SMoudy Ho #include <dt-bindings/power/mt8183-power.h> 894ad7b396SMoudy Ho #include <dt-bindings/memory/mt8183-larb-port.h> 904ad7b396SMoudy Ho 914ad7b396SMoudy Ho mdp3_rdma0: mdp3-rdma0@14001000 { 924ad7b396SMoudy Ho compatible = "mediatek,mt8183-mdp3-rdma"; 934ad7b396SMoudy Ho reg = <0x14001000 0x1000>; 944ad7b396SMoudy Ho mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 954ad7b396SMoudy Ho mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 964ad7b396SMoudy Ho <CMDQ_EVENT_MDP_RDMA0_EOF>; 974ad7b396SMoudy Ho power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 984ad7b396SMoudy Ho clocks = <&mmsys CLK_MM_MDP_RDMA0>, 994ad7b396SMoudy Ho <&mmsys CLK_MM_MDP_RSZ1>; 1004ad7b396SMoudy Ho iommus = <&iommu>; 1014ad7b396SMoudy Ho mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, 1024ad7b396SMoudy Ho <&gce 21 CMDQ_THR_PRIO_LOWEST>; 1034ad7b396SMoudy Ho }; 104