14ad7b396SMoudy Ho# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24ad7b396SMoudy Ho%YAML 1.2 34ad7b396SMoudy Ho--- 44ad7b396SMoudy Ho$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# 54ad7b396SMoudy Ho$schema: http://devicetree.org/meta-schemas/core.yaml# 64ad7b396SMoudy Ho 74ad7b396SMoudy Hotitle: MediaTek Read Direct Memory Access 84ad7b396SMoudy Ho 94ad7b396SMoudy Homaintainers: 104ad7b396SMoudy Ho - Matthias Brugger <matthias.bgg@gmail.com> 114ad7b396SMoudy Ho - Moudy Ho <moudy.ho@mediatek.com> 124ad7b396SMoudy Ho 134ad7b396SMoudy Hodescription: | 144ad7b396SMoudy Ho MediaTek Read Direct Memory Access(RDMA) component used to do read DMA. 154ad7b396SMoudy Ho It contains one line buffer to store the sufficient pixel data, and 164ad7b396SMoudy Ho must be siblings to the central MMSYS_CONFIG node. 174ad7b396SMoudy Ho For a description of the MMSYS_CONFIG binding, see 184ad7b396SMoudy Ho Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 194ad7b396SMoudy Ho for details. 204ad7b396SMoudy Ho 214ad7b396SMoudy Hoproperties: 224ad7b396SMoudy Ho compatible: 23*3bae0d63SMoudy Ho oneOf: 24*3bae0d63SMoudy Ho - enum: 25*3bae0d63SMoudy Ho - mediatek,mt8183-mdp3-rdma 26*3bae0d63SMoudy Ho - mediatek,mt8195-vdo1-rdma 27*3bae0d63SMoudy Ho - items: 28*3bae0d63SMoudy Ho - const: mediatek,mt8188-vdo1-rdma 29*3bae0d63SMoudy Ho - const: mediatek,mt8195-vdo1-rdma 304ad7b396SMoudy Ho 314ad7b396SMoudy Ho reg: 324ad7b396SMoudy Ho maxItems: 1 334ad7b396SMoudy Ho 344ad7b396SMoudy Ho mediatek,gce-client-reg: 35ab190665SRob Herring $ref: /schemas/types.yaml#/definitions/phandle-array 364ad7b396SMoudy Ho items: 374ad7b396SMoudy Ho items: 384ad7b396SMoudy Ho - description: phandle of GCE 394ad7b396SMoudy Ho - description: GCE subsys id 404ad7b396SMoudy Ho - description: register offset 414ad7b396SMoudy Ho - description: register size 424ad7b396SMoudy Ho description: The register of client driver can be configured by gce with 434ad7b396SMoudy Ho 4 arguments defined in this property. Each GCE subsys id is mapping to 444ad7b396SMoudy Ho a client defined in the header include/dt-bindings/gce/<chip>-gce.h. 454ad7b396SMoudy Ho 464ad7b396SMoudy Ho mediatek,gce-events: 474ad7b396SMoudy Ho description: 484ad7b396SMoudy Ho The event id which is mapping to the specific hardware event signal 494ad7b396SMoudy Ho to gce. The event id is defined in the gce header 504ad7b396SMoudy Ho include/dt-bindings/gce/<chip>-gce.h of each chips. 514ad7b396SMoudy Ho $ref: /schemas/types.yaml#/definitions/uint32-array 524ad7b396SMoudy Ho 53a17cf4c6SAngeloGioacchino Del Regno mediatek,scp: 54a17cf4c6SAngeloGioacchino Del Regno $ref: /schemas/types.yaml#/definitions/phandle 55a17cf4c6SAngeloGioacchino Del Regno description: 56a17cf4c6SAngeloGioacchino Del Regno Phandle to the System Control Processor (SCP) used for initializing 57a17cf4c6SAngeloGioacchino Del Regno and stopping the MDP3, for sending frame data locations to the MDP3's 58a17cf4c6SAngeloGioacchino Del Regno VPU and to install Inter-Processor Interrupt handlers to control 59a17cf4c6SAngeloGioacchino Del Regno processing states. 60a17cf4c6SAngeloGioacchino Del Regno 614ad7b396SMoudy Ho power-domains: 624ad7b396SMoudy Ho maxItems: 1 634ad7b396SMoudy Ho 644ad7b396SMoudy Ho clocks: 654ad7b396SMoudy Ho items: 664ad7b396SMoudy Ho - description: RDMA clock 674ad7b396SMoudy Ho - description: RSZ clock 68*3bae0d63SMoudy Ho minItems: 1 694ad7b396SMoudy Ho 704ad7b396SMoudy Ho iommus: 714ad7b396SMoudy Ho maxItems: 1 724ad7b396SMoudy Ho 734ad7b396SMoudy Ho mboxes: 744ad7b396SMoudy Ho items: 754ad7b396SMoudy Ho - description: used for 1st data pipe from RDMA 764ad7b396SMoudy Ho - description: used for 2nd data pipe from RDMA 77*3bae0d63SMoudy Ho minItems: 1 78*3bae0d63SMoudy Ho 79*3bae0d63SMoudy Ho interrupts: 80*3bae0d63SMoudy Ho maxItems: 1 814ad7b396SMoudy Ho 82f5f185bfSMoudy Ho '#dma-cells': 83f5f185bfSMoudy Ho const: 1 84f5f185bfSMoudy Ho 854ad7b396SMoudy Horequired: 864ad7b396SMoudy Ho - compatible 874ad7b396SMoudy Ho - reg 884ad7b396SMoudy Ho - mediatek,gce-client-reg 894ad7b396SMoudy Ho - power-domains 904ad7b396SMoudy Ho - clocks 914ad7b396SMoudy Ho - iommus 92f5f185bfSMoudy Ho - '#dma-cells' 934ad7b396SMoudy Ho 94*3bae0d63SMoudy HoallOf: 95*3bae0d63SMoudy Ho - if: 96*3bae0d63SMoudy Ho properties: 97*3bae0d63SMoudy Ho compatible: 98*3bae0d63SMoudy Ho contains: 99*3bae0d63SMoudy Ho const: mediatek,mt8183-mdp3-rdma 100*3bae0d63SMoudy Ho 101*3bae0d63SMoudy Ho then: 102*3bae0d63SMoudy Ho properties: 103*3bae0d63SMoudy Ho clocks: 104*3bae0d63SMoudy Ho minItems: 2 105*3bae0d63SMoudy Ho 106*3bae0d63SMoudy Ho mboxes: 107*3bae0d63SMoudy Ho minItems: 2 108*3bae0d63SMoudy Ho 109*3bae0d63SMoudy Ho required: 110*3bae0d63SMoudy Ho - mboxes 111*3bae0d63SMoudy Ho - mediatek,gce-events 112*3bae0d63SMoudy Ho 113*3bae0d63SMoudy Ho - if: 114*3bae0d63SMoudy Ho properties: 115*3bae0d63SMoudy Ho compatible: 116*3bae0d63SMoudy Ho contains: 117*3bae0d63SMoudy Ho const: mediatek,mt8195-vdo1-rdma 118*3bae0d63SMoudy Ho 119*3bae0d63SMoudy Ho then: 120*3bae0d63SMoudy Ho properties: 121*3bae0d63SMoudy Ho clocks: 122*3bae0d63SMoudy Ho maxItems: 1 123*3bae0d63SMoudy Ho 1244ad7b396SMoudy HoadditionalProperties: false 1254ad7b396SMoudy Ho 1264ad7b396SMoudy Hoexamples: 1274ad7b396SMoudy Ho - | 1284ad7b396SMoudy Ho #include <dt-bindings/clock/mt8183-clk.h> 1294ad7b396SMoudy Ho #include <dt-bindings/gce/mt8183-gce.h> 1304ad7b396SMoudy Ho #include <dt-bindings/power/mt8183-power.h> 1314ad7b396SMoudy Ho #include <dt-bindings/memory/mt8183-larb-port.h> 1324ad7b396SMoudy Ho 133f5f185bfSMoudy Ho dma-controller@14001000 { 1344ad7b396SMoudy Ho compatible = "mediatek,mt8183-mdp3-rdma"; 1354ad7b396SMoudy Ho reg = <0x14001000 0x1000>; 1364ad7b396SMoudy Ho mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1374ad7b396SMoudy Ho mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1384ad7b396SMoudy Ho <CMDQ_EVENT_MDP_RDMA0_EOF>; 1394ad7b396SMoudy Ho power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1404ad7b396SMoudy Ho clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1414ad7b396SMoudy Ho <&mmsys CLK_MM_MDP_RSZ1>; 1424ad7b396SMoudy Ho iommus = <&iommu>; 1434ad7b396SMoudy Ho mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, 1444ad7b396SMoudy Ho <&gce 21 CMDQ_THR_PRIO_LOWEST>; 145f5f185bfSMoudy Ho #dma-cells = <1>; 1464ad7b396SMoudy Ho }; 147