1*c0d9644fSLad, Prabhakar* Texas Instruments TV7002 video decoder 2*c0d9644fSLad, Prabhakar 3*c0d9644fSLad, PrabhakarThe TVP7002 device supports digitizing of video and graphics signal in RGB and 4*c0d9644fSLad, PrabhakarYPbPr color space. 5*c0d9644fSLad, Prabhakar 6*c0d9644fSLad, PrabhakarRequired Properties : 7*c0d9644fSLad, Prabhakar- compatible : Must be "ti,tvp7002" 8*c0d9644fSLad, Prabhakar 9*c0d9644fSLad, PrabhakarOptional Properties: 10*c0d9644fSLad, Prabhakar- hsync-active: HSYNC Polarity configuration for the bus. Default value when 11*c0d9644fSLad, Prabhakar this property is not specified is <0>. 12*c0d9644fSLad, Prabhakar 13*c0d9644fSLad, Prabhakar- vsync-active: VSYNC Polarity configuration for the bus. Default value when 14*c0d9644fSLad, Prabhakar this property is not specified is <0>. 15*c0d9644fSLad, Prabhakar 16*c0d9644fSLad, Prabhakar- pclk-sample: Clock polarity of the bus. Default value when this property is 17*c0d9644fSLad, Prabhakar not specified is <0>. 18*c0d9644fSLad, Prabhakar 19*c0d9644fSLad, Prabhakar- sync-on-green-active: Active state of Sync-on-green signal property of the 20*c0d9644fSLad, Prabhakar endpoint. 21*c0d9644fSLad, Prabhakar 0 = Normal Operation (Active Low, Default) 22*c0d9644fSLad, Prabhakar 1 = Inverted operation 23*c0d9644fSLad, Prabhakar 24*c0d9644fSLad, Prabhakar- field-even-active: Active-high Field ID output polarity control of the bus. 25*c0d9644fSLad, Prabhakar Under normal operation, the field ID output is set to logic 1 for an odd field 26*c0d9644fSLad, Prabhakar (field 1) and set to logic 0 for an even field (field 0). 27*c0d9644fSLad, Prabhakar 0 = Normal Operation (Active Low, Default) 28*c0d9644fSLad, Prabhakar 1 = FID output polarity inverted 29*c0d9644fSLad, Prabhakar 30*c0d9644fSLad, PrabhakarFor further reading of port node refer Documentation/devicetree/bindings/media/ 31*c0d9644fSLad, Prabhakarvideo-interfaces.txt. 32*c0d9644fSLad, Prabhakar 33*c0d9644fSLad, PrabhakarExample: 34*c0d9644fSLad, Prabhakar 35*c0d9644fSLad, Prabhakar i2c0@1c22000 { 36*c0d9644fSLad, Prabhakar ... 37*c0d9644fSLad, Prabhakar ... 38*c0d9644fSLad, Prabhakar tvp7002@5c { 39*c0d9644fSLad, Prabhakar compatible = "ti,tvp7002"; 40*c0d9644fSLad, Prabhakar reg = <0x5c>; 41*c0d9644fSLad, Prabhakar 42*c0d9644fSLad, Prabhakar port { 43*c0d9644fSLad, Prabhakar tvp7002_1: endpoint { 44*c0d9644fSLad, Prabhakar hsync-active = <1>; 45*c0d9644fSLad, Prabhakar vsync-active = <1>; 46*c0d9644fSLad, Prabhakar pclk-sample = <0>; 47*c0d9644fSLad, Prabhakar sync-on-green-active = <1>; 48*c0d9644fSLad, Prabhakar field-even-active = <0>; 49*c0d9644fSLad, Prabhakar }; 50*c0d9644fSLad, Prabhakar }; 51*c0d9644fSLad, Prabhakar }; 52*c0d9644fSLad, Prabhakar ... 53*c0d9644fSLad, Prabhakar }; 54