xref: /linux/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence MIPI-CSI2 RX controller
8
9maintainers:
10  - Maxime Ripard <mripard@kernel.org>
11
12description:
13  The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
14  lanes in input, and 4 different pixel streams in output.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - starfive,jh7110-csi2rx
21          - ti,j721e-csi2rx
22      - const: cdns,csi2rx
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 2
29
30  interrupt-names:
31    items:
32      - const: error_irq
33      - const: irq
34
35  clocks:
36    items:
37      - description: CSI2Rx system clock
38      - description: Gated Register bank clock for APB interface
39      - description: pixel Clock for Stream interface 0
40      - description: pixel Clock for Stream interface 1
41      - description: pixel Clock for Stream interface 2
42      - description: pixel Clock for Stream interface 3
43
44  clock-names:
45    items:
46      - const: sys_clk
47      - const: p_clk
48      - const: pixel_if0_clk
49      - const: pixel_if1_clk
50      - const: pixel_if2_clk
51      - const: pixel_if3_clk
52
53  resets:
54    items:
55      - description: CSI2Rx system reset
56      - description: Gated Register bank reset for APB interface
57      - description: pixel reset for Stream interface 0
58      - description: pixel reset for Stream interface 1
59      - description: pixel reset for Stream interface 2
60      - description: pixel reset for Stream interface 3
61
62  reset-names:
63    items:
64      - const: sys
65      - const: reg_bank
66      - const: pixel_if0
67      - const: pixel_if1
68      - const: pixel_if2
69      - const: pixel_if3
70
71  phys:
72    maxItems: 1
73    description: MIPI D-PHY
74
75  phy-names:
76    items:
77      - const: dphy
78
79  ports:
80    $ref: /schemas/graph.yaml#/properties/ports
81
82    properties:
83      port@0:
84        $ref: /schemas/graph.yaml#/$defs/port-base
85        unevaluatedProperties: false
86        description:
87          Input port node, single endpoint describing the CSI-2 transmitter.
88
89        properties:
90          endpoint:
91            $ref: video-interfaces.yaml#
92            unevaluatedProperties: false
93
94            properties:
95              bus-type:
96                const: 4
97
98              clock-lanes:
99                const: 0
100
101              data-lanes:
102                minItems: 1
103                maxItems: 4
104                items:
105                  maximum: 4
106
107            required:
108              - data-lanes
109
110      port@1:
111        $ref: /schemas/graph.yaml#/properties/port
112        description:
113          Stream 0 Output port node
114
115      port@2:
116        $ref: /schemas/graph.yaml#/properties/port
117        description:
118          Stream 1 Output port node
119
120      port@3:
121        $ref: /schemas/graph.yaml#/properties/port
122        description:
123          Stream 2 Output port node
124
125      port@4:
126        $ref: /schemas/graph.yaml#/properties/port
127        description:
128          Stream 3 Output port node
129
130    required:
131      - port@0
132
133required:
134  - compatible
135  - reg
136  - clocks
137  - clock-names
138  - ports
139
140additionalProperties: false
141
142examples:
143  - |
144    csi@d060000 {
145        compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
146        reg = <0x0d060000 0x1000>;
147        clocks = <&byteclock 7>, <&byteclock 6>,
148                 <&coreclock 8>, <&coreclock 9>,
149                 <&coreclock 10>, <&coreclock 11>;
150        clock-names = "sys_clk", "p_clk",
151                      "pixel_if0_clk", "pixel_if1_clk",
152                      "pixel_if2_clk", "pixel_if3_clk";
153        resets = <&bytereset 9>, <&bytereset 4>,
154                 <&corereset 5>, <&corereset 6>,
155                 <&corereset 7>, <&corereset 8>;
156        reset-names = "sys", "reg_bank",
157                      "pixel_if0", "pixel_if1",
158                      "pixel_if2", "pixel_if3";
159        phys = <&csi_phy>;
160        phy-names = "dphy";
161
162        ports {
163                #address-cells = <1>;
164                #size-cells = <0>;
165
166                port@0 {
167                    reg = <0>;
168
169                    csi2rx_in_sensor: endpoint {
170                        remote-endpoint = <&sensor_out_csi2rx>;
171                        clock-lanes = <0>;
172                        data-lanes = <1 2>;
173                    };
174                };
175
176                port@1 {
177                    reg = <1>;
178
179                    csi2rx_out_grabber0: endpoint {
180                        remote-endpoint = <&grabber0_in_csi2rx>;
181                    };
182                };
183
184                port@2 {
185                    reg = <2>;
186
187                    csi2rx_out_grabber1: endpoint {
188                        remote-endpoint = <&grabber1_in_csi2rx>;
189                    };
190                };
191
192                port@3 {
193                    reg = <3>;
194
195                    csi2rx_out_grabber2: endpoint {
196                        remote-endpoint = <&grabber2_in_csi2rx>;
197                    };
198                };
199
200                port@4 {
201                    reg = <4>;
202
203                    csi2rx_out_grabber3: endpoint {
204                        remote-endpoint = <&grabber3_in_csi2rx>;
205                    };
206                };
207        };
208    };
209
210...
211