xref: /linux/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml (revision ae08124d1c7da38a805f6b742c93b9a1ca25e29c) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence MIPI-CSI2 RX controller
8
9maintainers:
10  - Maxime Ripard <mripard@kernel.org>
11
12description:
13  The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
14  lanes in input, and 4 different pixel streams in output.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - starfive,jh7110-csi2rx
21      - const: cdns,csi2rx
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    items:
28      - description: CSI2Rx system clock
29      - description: Gated Register bank clock for APB interface
30      - description: pixel Clock for Stream interface 0
31      - description: pixel Clock for Stream interface 1
32      - description: pixel Clock for Stream interface 2
33      - description: pixel Clock for Stream interface 3
34
35  clock-names:
36    items:
37      - const: sys_clk
38      - const: p_clk
39      - const: pixel_if0_clk
40      - const: pixel_if1_clk
41      - const: pixel_if2_clk
42      - const: pixel_if3_clk
43
44  resets:
45    items:
46      - description: CSI2Rx system reset
47      - description: Gated Register bank reset for APB interface
48      - description: pixel reset for Stream interface 0
49      - description: pixel reset for Stream interface 1
50      - description: pixel reset for Stream interface 2
51      - description: pixel reset for Stream interface 3
52
53  reset-names:
54    items:
55      - const: sys
56      - const: reg_bank
57      - const: pixel_if0
58      - const: pixel_if1
59      - const: pixel_if2
60      - const: pixel_if3
61
62  phys:
63    maxItems: 1
64    description: MIPI D-PHY
65
66  phy-names:
67    items:
68      - const: dphy
69
70  ports:
71    $ref: /schemas/graph.yaml#/properties/ports
72
73    properties:
74      port@0:
75        $ref: /schemas/graph.yaml#/$defs/port-base
76        unevaluatedProperties: false
77        description:
78          Input port node, single endpoint describing the CSI-2 transmitter.
79
80        properties:
81          endpoint:
82            $ref: video-interfaces.yaml#
83            unevaluatedProperties: false
84
85            properties:
86              bus-type:
87                const: 4
88
89              clock-lanes:
90                const: 0
91
92              data-lanes:
93                minItems: 1
94                maxItems: 4
95                items:
96                  maximum: 4
97
98            required:
99              - data-lanes
100
101      port@1:
102        $ref: /schemas/graph.yaml#/properties/port
103        description:
104          Stream 0 Output port node
105
106      port@2:
107        $ref: /schemas/graph.yaml#/properties/port
108        description:
109          Stream 1 Output port node
110
111      port@3:
112        $ref: /schemas/graph.yaml#/properties/port
113        description:
114          Stream 2 Output port node
115
116      port@4:
117        $ref: /schemas/graph.yaml#/properties/port
118        description:
119          Stream 3 Output port node
120
121    required:
122      - port@0
123
124required:
125  - compatible
126  - reg
127  - clocks
128  - clock-names
129  - ports
130
131additionalProperties: false
132
133examples:
134  - |
135    csi@d060000 {
136        compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
137        reg = <0x0d060000 0x1000>;
138        clocks = <&byteclock 7>, <&byteclock 6>,
139                 <&coreclock 8>, <&coreclock 9>,
140                 <&coreclock 10>, <&coreclock 11>;
141        clock-names = "sys_clk", "p_clk",
142                      "pixel_if0_clk", "pixel_if1_clk",
143                      "pixel_if2_clk", "pixel_if3_clk";
144        resets = <&bytereset 9>, <&bytereset 4>,
145                 <&corereset 5>, <&corereset 6>,
146                 <&corereset 7>, <&corereset 8>;
147        reset-names = "sys", "reg_bank",
148                      "pixel_if0", "pixel_if1",
149                      "pixel_if2", "pixel_if3";
150        phys = <&csi_phy>;
151        phy-names = "dphy";
152
153        ports {
154                #address-cells = <1>;
155                #size-cells = <0>;
156
157                port@0 {
158                    reg = <0>;
159
160                    csi2rx_in_sensor: endpoint {
161                        remote-endpoint = <&sensor_out_csi2rx>;
162                        clock-lanes = <0>;
163                        data-lanes = <1 2>;
164                    };
165                };
166
167                port@1 {
168                    reg = <1>;
169
170                    csi2rx_out_grabber0: endpoint {
171                        remote-endpoint = <&grabber0_in_csi2rx>;
172                    };
173                };
174
175                port@2 {
176                    reg = <2>;
177
178                    csi2rx_out_grabber1: endpoint {
179                        remote-endpoint = <&grabber1_in_csi2rx>;
180                    };
181                };
182
183                port@3 {
184                    reg = <3>;
185
186                    csi2rx_out_grabber2: endpoint {
187                        remote-endpoint = <&grabber2_in_csi2rx>;
188                    };
189                };
190
191                port@4 {
192                    reg = <4>;
193
194                    csi2rx_out_grabber3: endpoint {
195                        remote-endpoint = <&grabber3_in_csi2rx>;
196                    };
197                };
198        };
199    };
200
201...
202