19536cc94SJack Zhu# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 29536cc94SJack Zhu%YAML 1.2 39536cc94SJack Zhu--- 49536cc94SJack Zhu$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# 59536cc94SJack Zhu$schema: http://devicetree.org/meta-schemas/core.yaml# 69536cc94SJack Zhu 79536cc94SJack Zhutitle: Cadence MIPI-CSI2 RX controller 89536cc94SJack Zhu 99536cc94SJack Zhumaintainers: 109536cc94SJack Zhu - Maxime Ripard <mripard@kernel.org> 119536cc94SJack Zhu 129536cc94SJack Zhudescription: 139536cc94SJack Zhu The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI 149536cc94SJack Zhu lanes in input, and 4 different pixel streams in output. 159536cc94SJack Zhu 169536cc94SJack Zhuproperties: 179536cc94SJack Zhu compatible: 189536cc94SJack Zhu items: 199536cc94SJack Zhu - enum: 209536cc94SJack Zhu - starfive,jh7110-csi2rx 219536cc94SJack Zhu - const: cdns,csi2rx 229536cc94SJack Zhu 239536cc94SJack Zhu reg: 249536cc94SJack Zhu maxItems: 1 259536cc94SJack Zhu 269536cc94SJack Zhu clocks: 279536cc94SJack Zhu items: 289536cc94SJack Zhu - description: CSI2Rx system clock 299536cc94SJack Zhu - description: Gated Register bank clock for APB interface 309536cc94SJack Zhu - description: pixel Clock for Stream interface 0 319536cc94SJack Zhu - description: pixel Clock for Stream interface 1 329536cc94SJack Zhu - description: pixel Clock for Stream interface 2 339536cc94SJack Zhu - description: pixel Clock for Stream interface 3 349536cc94SJack Zhu 359536cc94SJack Zhu clock-names: 369536cc94SJack Zhu items: 379536cc94SJack Zhu - const: sys_clk 389536cc94SJack Zhu - const: p_clk 399536cc94SJack Zhu - const: pixel_if0_clk 409536cc94SJack Zhu - const: pixel_if1_clk 419536cc94SJack Zhu - const: pixel_if2_clk 429536cc94SJack Zhu - const: pixel_if3_clk 439536cc94SJack Zhu 44*ae08124dSJack Zhu resets: 45*ae08124dSJack Zhu items: 46*ae08124dSJack Zhu - description: CSI2Rx system reset 47*ae08124dSJack Zhu - description: Gated Register bank reset for APB interface 48*ae08124dSJack Zhu - description: pixel reset for Stream interface 0 49*ae08124dSJack Zhu - description: pixel reset for Stream interface 1 50*ae08124dSJack Zhu - description: pixel reset for Stream interface 2 51*ae08124dSJack Zhu - description: pixel reset for Stream interface 3 52*ae08124dSJack Zhu 53*ae08124dSJack Zhu reset-names: 54*ae08124dSJack Zhu items: 55*ae08124dSJack Zhu - const: sys 56*ae08124dSJack Zhu - const: reg_bank 57*ae08124dSJack Zhu - const: pixel_if0 58*ae08124dSJack Zhu - const: pixel_if1 59*ae08124dSJack Zhu - const: pixel_if2 60*ae08124dSJack Zhu - const: pixel_if3 61*ae08124dSJack Zhu 629536cc94SJack Zhu phys: 639536cc94SJack Zhu maxItems: 1 649536cc94SJack Zhu description: MIPI D-PHY 659536cc94SJack Zhu 669536cc94SJack Zhu phy-names: 679536cc94SJack Zhu items: 689536cc94SJack Zhu - const: dphy 699536cc94SJack Zhu 709536cc94SJack Zhu ports: 719536cc94SJack Zhu $ref: /schemas/graph.yaml#/properties/ports 729536cc94SJack Zhu 739536cc94SJack Zhu properties: 749536cc94SJack Zhu port@0: 759536cc94SJack Zhu $ref: /schemas/graph.yaml#/$defs/port-base 769536cc94SJack Zhu unevaluatedProperties: false 779536cc94SJack Zhu description: 789536cc94SJack Zhu Input port node, single endpoint describing the CSI-2 transmitter. 799536cc94SJack Zhu 809536cc94SJack Zhu properties: 819536cc94SJack Zhu endpoint: 829536cc94SJack Zhu $ref: video-interfaces.yaml# 839536cc94SJack Zhu unevaluatedProperties: false 849536cc94SJack Zhu 859536cc94SJack Zhu properties: 869536cc94SJack Zhu bus-type: 879536cc94SJack Zhu const: 4 889536cc94SJack Zhu 899536cc94SJack Zhu clock-lanes: 909536cc94SJack Zhu const: 0 919536cc94SJack Zhu 929536cc94SJack Zhu data-lanes: 939536cc94SJack Zhu minItems: 1 949536cc94SJack Zhu maxItems: 4 959536cc94SJack Zhu items: 969536cc94SJack Zhu maximum: 4 979536cc94SJack Zhu 989536cc94SJack Zhu required: 999536cc94SJack Zhu - data-lanes 1009536cc94SJack Zhu 1019536cc94SJack Zhu port@1: 1029536cc94SJack Zhu $ref: /schemas/graph.yaml#/properties/port 1039536cc94SJack Zhu description: 1049536cc94SJack Zhu Stream 0 Output port node 1059536cc94SJack Zhu 1069536cc94SJack Zhu port@2: 1079536cc94SJack Zhu $ref: /schemas/graph.yaml#/properties/port 1089536cc94SJack Zhu description: 1099536cc94SJack Zhu Stream 1 Output port node 1109536cc94SJack Zhu 1119536cc94SJack Zhu port@3: 1129536cc94SJack Zhu $ref: /schemas/graph.yaml#/properties/port 1139536cc94SJack Zhu description: 1149536cc94SJack Zhu Stream 2 Output port node 1159536cc94SJack Zhu 1169536cc94SJack Zhu port@4: 1179536cc94SJack Zhu $ref: /schemas/graph.yaml#/properties/port 1189536cc94SJack Zhu description: 1199536cc94SJack Zhu Stream 3 Output port node 1209536cc94SJack Zhu 1219536cc94SJack Zhu required: 1229536cc94SJack Zhu - port@0 1239536cc94SJack Zhu 1249536cc94SJack Zhurequired: 1259536cc94SJack Zhu - compatible 1269536cc94SJack Zhu - reg 1279536cc94SJack Zhu - clocks 1289536cc94SJack Zhu - clock-names 1299536cc94SJack Zhu - ports 1309536cc94SJack Zhu 1319536cc94SJack ZhuadditionalProperties: false 1329536cc94SJack Zhu 1339536cc94SJack Zhuexamples: 1349536cc94SJack Zhu - | 1359536cc94SJack Zhu csi@d060000 { 1369536cc94SJack Zhu compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; 1379536cc94SJack Zhu reg = <0x0d060000 0x1000>; 1389536cc94SJack Zhu clocks = <&byteclock 7>, <&byteclock 6>, 1399536cc94SJack Zhu <&coreclock 8>, <&coreclock 9>, 1409536cc94SJack Zhu <&coreclock 10>, <&coreclock 11>; 1419536cc94SJack Zhu clock-names = "sys_clk", "p_clk", 1429536cc94SJack Zhu "pixel_if0_clk", "pixel_if1_clk", 1439536cc94SJack Zhu "pixel_if2_clk", "pixel_if3_clk"; 144*ae08124dSJack Zhu resets = <&bytereset 9>, <&bytereset 4>, 145*ae08124dSJack Zhu <&corereset 5>, <&corereset 6>, 146*ae08124dSJack Zhu <&corereset 7>, <&corereset 8>; 147*ae08124dSJack Zhu reset-names = "sys", "reg_bank", 148*ae08124dSJack Zhu "pixel_if0", "pixel_if1", 149*ae08124dSJack Zhu "pixel_if2", "pixel_if3"; 1509536cc94SJack Zhu phys = <&csi_phy>; 1519536cc94SJack Zhu phy-names = "dphy"; 1529536cc94SJack Zhu 1539536cc94SJack Zhu ports { 1549536cc94SJack Zhu #address-cells = <1>; 1559536cc94SJack Zhu #size-cells = <0>; 1569536cc94SJack Zhu 1579536cc94SJack Zhu port@0 { 1589536cc94SJack Zhu reg = <0>; 1599536cc94SJack Zhu 1609536cc94SJack Zhu csi2rx_in_sensor: endpoint { 1619536cc94SJack Zhu remote-endpoint = <&sensor_out_csi2rx>; 1629536cc94SJack Zhu clock-lanes = <0>; 1639536cc94SJack Zhu data-lanes = <1 2>; 1649536cc94SJack Zhu }; 1659536cc94SJack Zhu }; 1669536cc94SJack Zhu 1679536cc94SJack Zhu port@1 { 1689536cc94SJack Zhu reg = <1>; 1699536cc94SJack Zhu 1709536cc94SJack Zhu csi2rx_out_grabber0: endpoint { 1719536cc94SJack Zhu remote-endpoint = <&grabber0_in_csi2rx>; 1729536cc94SJack Zhu }; 1739536cc94SJack Zhu }; 1749536cc94SJack Zhu 1759536cc94SJack Zhu port@2 { 1769536cc94SJack Zhu reg = <2>; 1779536cc94SJack Zhu 1789536cc94SJack Zhu csi2rx_out_grabber1: endpoint { 1799536cc94SJack Zhu remote-endpoint = <&grabber1_in_csi2rx>; 1809536cc94SJack Zhu }; 1819536cc94SJack Zhu }; 1829536cc94SJack Zhu 1839536cc94SJack Zhu port@3 { 1849536cc94SJack Zhu reg = <3>; 1859536cc94SJack Zhu 1869536cc94SJack Zhu csi2rx_out_grabber2: endpoint { 1879536cc94SJack Zhu remote-endpoint = <&grabber2_in_csi2rx>; 1889536cc94SJack Zhu }; 1899536cc94SJack Zhu }; 1909536cc94SJack Zhu 1919536cc94SJack Zhu port@4 { 1929536cc94SJack Zhu reg = <4>; 1939536cc94SJack Zhu 1949536cc94SJack Zhu csi2rx_out_grabber3: endpoint { 1959536cc94SJack Zhu remote-endpoint = <&grabber3_in_csi2rx>; 1969536cc94SJack Zhu }; 1979536cc94SJack Zhu }; 1989536cc94SJack Zhu }; 1999536cc94SJack Zhu }; 2009536cc94SJack Zhu 2019536cc94SJack Zhu... 202