1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13description: |- 14 The Allwinner A10 and later has a CMOS Sensor Interface to retrieve 15 frames from a parallel or BT656 sensor. 16 17properties: 18 compatible: 19 oneOf: 20 - const: allwinner,sun4i-a10-csi1 21 - const: allwinner,sun7i-a20-csi0 22 - items: 23 - const: allwinner,sun7i-a20-csi1 24 - const: allwinner,sun4i-a10-csi1 25 - items: 26 - const: allwinner,sun8i-r40-csi0 27 - const: allwinner,sun7i-a20-csi0 28 29 reg: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 1 34 35 clocks: 36 minItems: 2 37 maxItems: 3 38 items: 39 - description: The CSI interface clock 40 - description: The CSI ISP clock 41 - description: The CSI DRAM clock 42 43 clock-names: 44 minItems: 2 45 maxItems: 3 46 items: 47 - const: bus 48 - const: isp 49 - const: ram 50 51 resets: 52 maxItems: 1 53 54 # See ./video-interfaces.txt for details 55 port: 56 type: object 57 additionalProperties: false 58 59 properties: 60 endpoint: 61 type: object 62 63 properties: 64 bus-width: 65 enum: [8, 16] 66 67 data-active: true 68 hsync-active: true 69 pclk-sample: true 70 remote-endpoint: true 71 vsync-active: true 72 73 required: 74 - bus-width 75 - data-active 76 - hsync-active 77 - pclk-sample 78 - remote-endpoint 79 - vsync-active 80 81 required: 82 - endpoint 83 84required: 85 - compatible 86 - reg 87 - interrupts 88 - clocks 89 90additionalProperties: false 91 92examples: 93 - | 94 #include <dt-bindings/interrupt-controller/arm-gic.h> 95 #include <dt-bindings/clock/sun7i-a20-ccu.h> 96 #include <dt-bindings/reset/sun4i-a10-ccu.h> 97 98 csi0: csi@1c09000 { 99 compatible = "allwinner,sun7i-a20-csi0"; 100 reg = <0x01c09000 0x1000>; 101 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; 103 clock-names = "bus", "isp", "ram"; 104 resets = <&ccu RST_CSI0>; 105 106 port { 107 csi_from_ov5640: endpoint { 108 remote-endpoint = <&ov5640_to_csi>; 109 bus-width = <8>; 110 hsync-active = <1>; /* Active high */ 111 vsync-active = <0>; /* Active low */ 112 data-active = <1>; /* Active high */ 113 pclk-sample = <1>; /* Rising */ 114 }; 115 }; 116 }; 117 118... 119