1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13description: |- 14 The Allwinner A10 and later has a CMOS Sensor Interface to retrieve 15 frames from a parallel or BT656 sensor. 16 17properties: 18 compatible: 19 oneOf: 20 - const: allwinner,sun4i-a10-csi1 21 - const: allwinner,sun7i-a20-csi0 22 - items: 23 - const: allwinner,sun7i-a20-csi1 24 - const: allwinner,sun4i-a10-csi1 25 - items: 26 - const: allwinner,sun8i-r40-csi0 27 - const: allwinner,sun7i-a20-csi0 28 29 reg: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 1 34 35 clocks: 36 oneOf: 37 - items: 38 - description: The CSI interface clock 39 - description: The CSI DRAM clock 40 41 - items: 42 - description: The CSI interface clock 43 - description: The CSI ISP clock 44 - description: The CSI DRAM clock 45 46 clock-names: 47 oneOf: 48 - items: 49 - const: bus 50 - const: ram 51 52 - items: 53 - const: bus 54 - const: isp 55 - const: ram 56 57 resets: 58 maxItems: 1 59 60 # FIXME: This should be made required eventually once every SoC will 61 # have the MBUS declared. 62 interconnects: 63 maxItems: 1 64 65 # FIXME: This should be made required eventually once every SoC will 66 # have the MBUS declared. 67 interconnect-names: 68 const: dma-mem 69 70 port: 71 $ref: /schemas/graph.yaml#/$defs/port-base 72 additionalProperties: false 73 74 properties: 75 endpoint: 76 $ref: video-interfaces.yaml# 77 unevaluatedProperties: false 78 79 properties: 80 bus-width: 81 enum: [8, 16] 82 83 data-active: true 84 hsync-active: true 85 pclk-sample: true 86 vsync-active: true 87 88 required: 89 - bus-width 90 - data-active 91 - hsync-active 92 - pclk-sample 93 - vsync-active 94 95required: 96 - compatible 97 - reg 98 - interrupts 99 - clocks 100 101additionalProperties: false 102 103examples: 104 - | 105 #include <dt-bindings/interrupt-controller/arm-gic.h> 106 #include <dt-bindings/clock/sun7i-a20-ccu.h> 107 #include <dt-bindings/reset/sun4i-a10-ccu.h> 108 109 csi0: csi@1c09000 { 110 compatible = "allwinner,sun7i-a20-csi0"; 111 reg = <0x01c09000 0x1000>; 112 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; 114 clock-names = "bus", "isp", "ram"; 115 resets = <&ccu RST_CSI0>; 116 117 port { 118 csi_from_ov5640: endpoint { 119 remote-endpoint = <&ov5640_to_csi>; 120 bus-width = <8>; 121 hsync-active = <1>; /* Active high */ 122 vsync-active = <0>; /* Active low */ 123 data-active = <1>; /* Active high */ 124 pclk-sample = <1>; /* Rising */ 125 }; 126 }; 127 }; 128 129... 130