1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: STMicroelectronics STM32 IPC controller bindings 8 9description: 10 The IPCC block provides a non blocking signaling mechanism to post and 11 retrieve messages in an atomic way between two processors. 12 It provides the signaling for N bidirectionnal channels. The number of 13 channels (N) can be read from a dedicated register. 14 15maintainers: 16 - Fabien Dessenne <fabien.dessenne@foss.st.com> 17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 18 19properties: 20 compatible: 21 const: st,stm32mp1-ipcc 22 23 reg: 24 maxItems: 1 25 26 clocks: 27 maxItems: 1 28 29 interrupts: 30 items: 31 - description: rx channel occupied 32 - description: tx channel free 33 - description: wakeup source 34 minItems: 2 35 36 interrupt-names: 37 items: 38 - const: rx 39 - const: tx 40 - const: wakeup 41 minItems: 2 42 43 wakeup-source: true 44 45 "#mbox-cells": 46 const: 1 47 48 st,proc-id: 49 description: Processor id using the mailbox (0 or 1) 50 $ref: /schemas/types.yaml#/definitions/uint32 51 enum: [0, 1] 52 53required: 54 - compatible 55 - reg 56 - st,proc-id 57 - clocks 58 - interrupt-names 59 - "#mbox-cells" 60 - interrupts 61 62additionalProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/interrupt-controller/arm-gic.h> 67 #include <dt-bindings/clock/stm32mp1-clks.h> 68 ipcc: mailbox@4c001000 { 69 compatible = "st,stm32mp1-ipcc"; 70 #mbox-cells = <1>; 71 reg = <0x4c001000 0x400>; 72 st,proc-id = <0>; 73 interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, 74 <&intc GIC_SPI 101 IRQ_TYPE_NONE>, 75 <&aiec 62 1>; 76 interrupt-names = "rx", "tx", "wakeup"; 77 clocks = <&rcc_clk IPCC>; 78 wakeup-source; 79 }; 80 81... 82