1*a7065bc3SCaesar WangRockchip mailbox 2*a7065bc3SCaesar Wang 3*a7065bc3SCaesar WangThe Rockchip mailbox is used by the Rockchip CPU cores to communicate 4*a7065bc3SCaesar Wangrequests to MCU processor. 5*a7065bc3SCaesar Wang 6*a7065bc3SCaesar WangRefer to ./mailbox.txt for generic information about mailbox device-tree 7*a7065bc3SCaesar Wangbindings. 8*a7065bc3SCaesar Wang 9*a7065bc3SCaesar WangRequired properties: 10*a7065bc3SCaesar Wang 11*a7065bc3SCaesar Wang - compatible: should be one of the following. 12*a7065bc3SCaesar Wang - "rockchip,rk3368-mbox" for rk3368 13*a7065bc3SCaesar Wang - reg: physical base address of the controller and length of memory mapped 14*a7065bc3SCaesar Wang region. 15*a7065bc3SCaesar Wang - interrupts: The interrupt number to the cpu. The interrupt specifier format 16*a7065bc3SCaesar Wang depends on the interrupt controller. 17*a7065bc3SCaesar Wang - #mbox-cells: Common mailbox binding property to identify the number 18*a7065bc3SCaesar Wang of cells required for the mailbox specifier. Should be 1 19*a7065bc3SCaesar Wang 20*a7065bc3SCaesar WangExample: 21*a7065bc3SCaesar Wang-------- 22*a7065bc3SCaesar Wang 23*a7065bc3SCaesar Wang/* RK3368 */ 24*a7065bc3SCaesar Wangmbox: mbox@ff6b0000 { 25*a7065bc3SCaesar Wang compatible = "rockchip,rk3368-mailbox"; 26*a7065bc3SCaesar Wang reg = <0x0 0xff6b0000 0x0 0x1000>, 27*a7065bc3SCaesar Wang interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 28*a7065bc3SCaesar Wang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 29*a7065bc3SCaesar Wang <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 30*a7065bc3SCaesar Wang <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 31*a7065bc3SCaesar Wang #mbox-cells = <1>; 32*a7065bc3SCaesar Wang}; 33