xref: /linux/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml (revision 90d32e92011eaae8e70a9169b4e7acf4ca8f9d3a) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description:
13  The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14  to route interrupts across various subsystems. It involves a three-level
15  addressing scheme called protocol, client and signal. For example, consider an
16  entity on the Application Processor Subsystem (APSS) that wants to listen to
17  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18  a case, the client would be Modem (client-id is 2) and the signal would be
19  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21  for the list of such IDs.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - qcom,qdu1000-ipcc
28          - qcom,sa8775p-ipcc
29          - qcom,sc7280-ipcc
30          - qcom,sc8280xp-ipcc
31          - qcom,sdx75-ipcc
32          - qcom,sm6350-ipcc
33          - qcom,sm6375-ipcc
34          - qcom,sm8250-ipcc
35          - qcom,sm8350-ipcc
36          - qcom,sm8450-ipcc
37          - qcom,sm8550-ipcc
38          - qcom,sm8650-ipcc
39          - qcom,x1e80100-ipcc
40      - const: qcom,ipcc
41
42  reg:
43    maxItems: 1
44
45  interrupts:
46    maxItems: 1
47
48  interrupt-controller: true
49
50  "#interrupt-cells":
51    const: 3
52    description:
53      The first cell is the client-id, the second cell is the signal-id and the
54      third cell is the interrupt type.
55
56  "#mbox-cells":
57    const: 2
58    description:
59      The first cell is the client-id, and the second cell is the signal-id.
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - interrupt-controller
66  - "#interrupt-cells"
67  - "#mbox-cells"
68
69additionalProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/interrupt-controller/arm-gic.h>
74    #include <dt-bindings/mailbox/qcom-ipcc.h>
75
76    mailbox@408000 {
77        compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
78        reg = <0x408000 0x1000>;
79        interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
80        interrupt-controller;
81        #interrupt-cells = <3>;
82        #mbox-cells = <2>;
83    };
84