xref: /linux/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml (revision 805185b7c7a1069e407b6f7b3bc98e44d415f484) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description:
13  The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14  to route interrupts across various subsystems. It involves a three-level
15  addressing scheme called protocol, client and signal. For example, consider an
16  entity on the Application Processor Subsystem (APSS) that wants to listen to
17  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18  a case, the client would be Modem (client-id is 2) and the signal would be
19  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21  for the list of such IDs.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - qcom,eliza-ipcc
28          - qcom,glymur-ipcc
29          - qcom,hawi-ipcc
30          - qcom,kaanapali-ipcc
31          - qcom,maili-ipcc
32          - qcom,milos-ipcc
33          - qcom,qcs8300-ipcc
34          - qcom,qdu1000-ipcc
35          - qcom,sa8255p-ipcc
36          - qcom,sa8775p-ipcc
37          - qcom,sar2130p-ipcc
38          - qcom,sc7280-ipcc
39          - qcom,sc8280xp-ipcc
40          - qcom,sdx75-ipcc
41          - qcom,sm6350-ipcc
42          - qcom,sm6375-ipcc
43          - qcom,sm8250-ipcc
44          - qcom,sm8350-ipcc
45          - qcom,sm8450-ipcc
46          - qcom,sm8550-ipcc
47          - qcom,sm8650-ipcc
48          - qcom,sm8750-ipcc
49          - qcom,x1e80100-ipcc
50      - const: qcom,ipcc
51
52  reg:
53    maxItems: 1
54
55  interrupts:
56    maxItems: 1
57
58  interrupt-controller: true
59
60  "#interrupt-cells":
61    const: 3
62    description:
63      The first cell is the client-id, the second cell is the signal-id and the
64      third cell is the interrupt type.
65
66  "#mbox-cells":
67    const: 2
68    description:
69      The first cell is the client-id, and the second cell is the signal-id.
70
71required:
72  - compatible
73  - reg
74  - interrupts
75  - interrupt-controller
76  - "#interrupt-cells"
77  - "#mbox-cells"
78
79additionalProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/interrupt-controller/arm-gic.h>
84    #include <dt-bindings/mailbox/qcom-ipcc.h>
85
86    mailbox@408000 {
87        compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
88        reg = <0x408000 0x1000>;
89        interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
90        interrupt-controller;
91        #interrupt-cells = <3>;
92        #mbox-cells = <2>;
93    };
94