xref: /linux/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml (revision 24bce201d79807b668bf9d9e0aca801c5c0d5f78) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description:
13  The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14  to route interrupts across various subsystems. It involves a three-level
15  addressing scheme called protocol, client and signal. For example, consider an
16  entity on the Application Processor Subsystem (APSS) that wants to listen to
17  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18  a case, the client would be Modem (client-id is 2) and the signal would be
19  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21  for the list of such IDs.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - qcom,sm6350-ipcc
28          - qcom,sm8250-ipcc
29          - qcom,sm8350-ipcc
30          - qcom,sm8450-ipcc
31          - qcom,sc7280-ipcc
32      - const: qcom,ipcc
33
34  reg:
35    maxItems: 1
36
37  interrupts:
38    maxItems: 1
39
40  interrupt-controller: true
41
42  "#interrupt-cells":
43    const: 3
44    description:
45      The first cell is the client-id, the second cell is the signal-id and the
46      third cell is the interrupt type.
47
48  "#mbox-cells":
49    const: 2
50    description:
51      The first cell is the client-id, and the second cell is the signal-id.
52
53required:
54  - compatible
55  - reg
56  - interrupts
57  - interrupt-controller
58  - "#interrupt-cells"
59  - "#mbox-cells"
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/interrupt-controller/arm-gic.h>
66    #include <dt-bindings/mailbox/qcom-ipcc.h>
67
68    mailbox@408000 {
69        compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
70        reg = <0x408000 0x1000>;
71        interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
72        interrupt-controller;
73        #interrupt-cells = <3>;
74        #mbox-cells = <2>;
75    };
76